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annotate simple_console.txt @ 4:8170d60f188b

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Added basic rendering timing outline and made some other minor spec changes
author Michael Pavone <pavone@retrodev.com>
date Fri, 25 Mar 2016 19:26:23 -0700
parents 08b69e3f9f17
children 18b66690ae13
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0
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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1 Key:
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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2 1 = literal 1 bit
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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3 0 = literal 0 bit
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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4 O = opcode bit
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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5 D = destination register bit
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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6 A = source A register bit
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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7 B = source B register bit
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8
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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9 DDDD AAAA BBBB OOOO
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10
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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11 0: ldim
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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12 D = destination reg
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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13 A and B form 8-bit immediate value
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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14 1: ldimh
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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15 D = destination reg
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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16 A and B form 8-bit immediate value
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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17 2: ld8
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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18 3: ld16
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19 4: str8
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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20 5: str16
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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21 6: add
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22 7: adc
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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23 8: and
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24 9: or
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25 A: xor
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26 B: lsl
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27 C: lsr
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28 D: asr
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29 E: bcc
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30 F: single source
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31
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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32
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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33
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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34 DDDD AAAA OOOO 1111
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35
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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36 single source
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37
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38 0: mov
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39 1: neg
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40 2: not
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41 3: cmp
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42 4: call
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43 A = register containing pointer to function
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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44 D = register that will store PC value
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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45 5: swap
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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46 6: in
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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47 7: out
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48 8: ini
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49 9: outi
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50 A: addi
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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51 B: andi
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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52 C: ori
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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53 D: ls[lr]i
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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54 MSB of AAAA determines direction
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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55 LS 3 bits determines magnitude
2
6204c81e2933 Revert changes to handling of immediate versions of bitwise instructions. Replace asri with cmpi.
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56 E: cmpi
0
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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57 F: single reg
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58
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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59
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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60 DDDD OOOO 1111 1111
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61
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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62 0: reti - return from interrupt, D = register to restore from uer
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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63 1: trap
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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64 2: trapi
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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65 3: getepc
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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66 4: setepc
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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67 5: getesr
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68 6: setesr
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69 7: getenum
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70 8: setenum
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71 9: getuer
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72 A: setuer
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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73 B: getenum
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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74 C: setenum
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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75 E: invalid
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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76 F: invalid
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77
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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78
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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79 Registers:
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80
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81 r0 - r12 : general purpose
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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82 r13 : technically general purpose, but canonically the stack register
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83 r14 : PC
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84 r15 : status register
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85
3
08b69e3f9f17 Fleshed out the video hardware design somewhat
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86 Special Registers
08b69e3f9f17 Fleshed out the video hardware design somewhat
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87 epc - Exception PC - Stores PC value to resume to when entering an exception handler
08b69e3f9f17 Fleshed out the video hardware design somewhat
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88 esr - Exception SR - same as above, but for SR
08b69e3f9f17 Fleshed out the video hardware design somewhat
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89 eur - Exceptuion User Reg - reg for temporary storage of a reg in a handler, intended to be used for the stack pointer
08b69e3f9f17 Fleshed out the video hardware design somewhat
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90 enum - Exception Number - holds the number of the most recent exception
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91
0
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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92 IO: Ports
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93
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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94 0: Controller 1
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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95 1: Controller 2
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96 2: Controller 3
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97 3: Controller 4
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98
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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99 4: Channel A Freq
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100 Load value for a 16-bit down-counter
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101 Polarity of output is switched on transition from 1 to 0
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102 Value is loaded on cycles where counter is 0
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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103 Special case value of 0 in this register forces polarity to positive
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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104 5: Channel B Freq
7e44f7d5810b Initial commit. CPU working well enough for simple hello world program.
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105 6: Channel C Freq
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106 7: Channel D Freq
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107
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108 8: Channel A/B Vol
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109 9: Channel C/D Vol
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110
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111 A: Timer Freq
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112 B: "Serial" Debug Port
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113
3
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114 C: Write Vertical Scroll : Read Vertical Position
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115 MMMM MCCC CCCC CFFF
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116 C = coarse scroll bit
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117 F = fine scroll bit
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118 M = mask bit
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119 controls which bits come directly from register
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120 and which bits come from the sum of the register
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121 and the current line number
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122
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123 D: Write Horizontal Scroll : Read Horizontal Position
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124 xxxx xxxC CCCC CFFF
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125 C = coarse scroll bit
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126 F = fine scroll bit
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127 x = unused
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128 E: Write Dest Address : Read Status
4
8170d60f188b Added basic rendering timing outline and made some other minor spec changes
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129 F: Write Data : Read ???
3
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130
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131
08b69e3f9f17 Fleshed out the video hardware design somewhat
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132 Name Table Start Address:
08b69e3f9f17 Fleshed out the video hardware design somewhat
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133 0VVV VVVV VHHH HHH0
08b69e3f9f17 Fleshed out the video hardware design somewhat
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134
08b69e3f9f17 Fleshed out the video hardware design somewhat
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135 V = Coarse scroll bit from vertical scroll value
08b69e3f9f17 Fleshed out the video hardware design somewhat
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136 H = Coarse scroll bit from horizontal scroll value
08b69e3f9f17 Fleshed out the video hardware design somewhat
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137
08b69e3f9f17 Fleshed out the video hardware design somewhat
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138 VDP Memory Map
08b69e3f9f17 Fleshed out the video hardware design somewhat
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139 0000 - 7FFF = Pattern/Name Table RAM
08b69e3f9f17 Fleshed out the video hardware design somewhat
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140 8000 - FDFF = unused, returns $FFFF
08b69e3f9f17 Fleshed out the video hardware design somewhat
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141 FE00 - FEFF = Sprite RAM
08b69e3f9f17 Fleshed out the video hardware design somewhat
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142 FF00 - FF7F = Palette RAM
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143 FF80 - FFFF = Palette RAM (mirror)
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144
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145 Another View -
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146 MSB determines whether destination is main RAM
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147 For MSB 1
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148 Next 7 MSB determines which special RAM is the destination
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149 Only values of 7E and 7F are valid for these bits at present
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150 8 LSB determine offset (1 LSB ignored)
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151
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152 Writing to Data port puts value into a one word FIFO
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153 Offset within memory type is increment when word is pulled from FIFO
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154 Writing to the FIFO when it is full will cause the existing entry to be overwritten
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155
3
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156
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157 Pattern Format:
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158 4bpp in an 8x8 tile arrangement
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159
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160
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161 Sprite Table Entry:
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162
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163 XXXXXXXX YYYYYYYY
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164 IXPVHSNN NNNNNNNN
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165
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166 S: size -- 0 = 8x8, 1 = 16x16
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167 P: Palette selector
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168 H: Horizontal flip
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169 V: Vertical flip
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170 I: Priority
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171 N: Name
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172 X: X position (left of screen = 16, right of screen = ?)
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173 Y: Y position (top of screen = 16, bottom of screen = 240)
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174
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175
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176 Name Table Entry:
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177
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178 IPPVHxNN NNNNNNNN
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179
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180 P: Palette selector
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181 H: Horizontal flip
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182 V: Vertical flip
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183 I: Priority
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184 N: Name
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185 x: Unused, should be set to 0
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186
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187 26.112 MHZ Clock
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188 Dot Clock Divider 4
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189 CPU Clock Divider 20 (assuming 1 cycle/instruction, 5 for 4 cycles/instruction)
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190 Audio Timer Divider 34
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191 Audio Output Divider 544
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192
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193 Alternatively 13.056 Mhz clock and cut the dividers in half
0
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194
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195
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196
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197 H-Counter goes from 0-415 and then wraps back to zero
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198 V-Counter goes from 0-261 and then wraps back to zero
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199 V-Counter increments when H-Counter wraps
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200
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201 Rendering Process:
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202 208 main VRAM access slots
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203 123 slots for background
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204 160-123 = 37 extra slots during active display
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205 48 slots during inactive display
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206 80 slots for sprite rendering
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207 5 slots remain for refresh or external access
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208
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209 Since sprite rendering needs to intrude on active display period,
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210 a double buffered line buffer is needed. Useful for VGA compatibility anyway
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211