Mercurial > repos > simple16
annotate simple_console.txt @ 0:7e44f7d5810b
Initial commit. CPU working well enough for simple hello world program.
author | Michael Pavone <pavone@retrodev.com> |
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date | Tue, 22 Mar 2016 22:44:02 -0700 |
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children | 6204c81e2933 |
rev | line source |
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0
7e44f7d5810b
Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
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1 Key: |
7e44f7d5810b
Initial commit. CPU working well enough for simple hello world program.
Michael Pavone <pavone@retrodev.com>
parents:
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2 1 = literal 1 bit |
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Initial commit. CPU working well enough for simple hello world program.
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3 0 = literal 0 bit |
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Initial commit. CPU working well enough for simple hello world program.
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4 O = opcode bit |
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Initial commit. CPU working well enough for simple hello world program.
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5 D = destination register bit |
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Initial commit. CPU working well enough for simple hello world program.
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6 A = source A register bit |
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Initial commit. CPU working well enough for simple hello world program.
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7 B = source B register bit |
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Initial commit. CPU working well enough for simple hello world program.
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8 |
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9 DDDD AAAA BBBB OOOO |
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10 |
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11 0: ldim |
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12 D = destination reg |
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Initial commit. CPU working well enough for simple hello world program.
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13 A and B form 8-bit immediate value |
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14 1: ldimh |
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15 D = destination reg |
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Initial commit. CPU working well enough for simple hello world program.
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16 A and B form 8-bit immediate value |
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17 2: ld8 |
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18 3: ld16 |
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19 4: str8 |
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20 5: str16 |
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21 6: add |
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22 7: adc |
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23 8: and |
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24 9: or |
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25 A: xor |
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26 B: lsl |
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27 C: lsr |
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28 D: asr |
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29 E: bcc |
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Initial commit. CPU working well enough for simple hello world program.
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30 F: single source |
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31 |
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32 |
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Initial commit. CPU working well enough for simple hello world program.
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33 |
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Initial commit. CPU working well enough for simple hello world program.
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34 DDDD AAAA OOOO 1111 |
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35 |
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Initial commit. CPU working well enough for simple hello world program.
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36 single source |
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Initial commit. CPU working well enough for simple hello world program.
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37 |
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Initial commit. CPU working well enough for simple hello world program.
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38 0: mov |
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Initial commit. CPU working well enough for simple hello world program.
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39 1: neg |
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40 2: not |
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41 3: cmp |
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42 4: call |
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Initial commit. CPU working well enough for simple hello world program.
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43 A = register containing pointer to function |
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Initial commit. CPU working well enough for simple hello world program.
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44 D = register that will store PC value |
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Initial commit. CPU working well enough for simple hello world program.
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45 5: swap |
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Initial commit. CPU working well enough for simple hello world program.
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46 6: in |
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Initial commit. CPU working well enough for simple hello world program.
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47 7: out |
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48 8: ini |
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Initial commit. CPU working well enough for simple hello world program.
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49 9: outi |
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50 A: addi |
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51 B: andi |
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52 C: ori |
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Initial commit. CPU working well enough for simple hello world program.
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53 D: ls[lr]i |
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Initial commit. CPU working well enough for simple hello world program.
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54 MSB of AAAA determines direction |
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Initial commit. CPU working well enough for simple hello world program.
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55 LS 3 bits determines magnitude |
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56 E: asri |
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57 F: single reg |
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58 |
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Initial commit. CPU working well enough for simple hello world program.
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59 |
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60 DDDD OOOO 1111 1111 |
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61 |
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62 0: reti - return from interrupt, D = register to restore from uer |
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Initial commit. CPU working well enough for simple hello world program.
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63 1: trap |
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64 2: trapi |
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65 3: getepc |
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66 4: setepc |
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67 5: getesr |
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68 6: setesr |
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69 7: getenum |
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70 8: setenum |
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71 9: getuer |
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72 A: setuer |
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73 B: getenum |
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74 C: setenum |
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75 E: invalid |
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76 F: invalid |
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77 |
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78 |
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Initial commit. CPU working well enough for simple hello world program.
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79 Registers: |
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80 |
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81 r0 - r12 : general purpose |
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82 r13 : technically general purpose, but canonically the stack register |
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83 r14 : PC |
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84 r15 : status register |
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85 |
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86 IO: Ports |
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87 |
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Initial commit. CPU working well enough for simple hello world program.
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88 0: Controller 1 |
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89 1: Controller 2 |
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90 2: Controller 3 |
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91 3: Controller 4 |
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92 |
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93 4: Channel A Freq |
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94 Load value for a 16-bit down-counter |
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95 Polarity of output is switched on transition from 1 to 0 |
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96 Value is loaded on cycles where counter is 0 |
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97 Special case value of 0 in this register forces polarity to positive |
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98 5: Channel B Freq |
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99 6: Channel C Freq |
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100 7: Channel D Freq |
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101 |
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102 8: Channel A/B Vol |
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103 9: Channel C/D Vol |
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104 |
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105 A: Timer Freq |
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106 B: "Serial" Debug Port |
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107 |
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108 D: Write Pallette Address : Read Vertical Position |
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109 E: Write Name Table Address : Read Horizontal Position |
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110 F: Write Sprite Table Address : Read Status? |
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111 |
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112 |
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113 |
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114 |
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115 |