log

age author description
Mon, 16 Sep 2013 09:44:22 -0700 Mike Pavone Partial fix for DMA copy
Sun, 15 Sep 2013 23:49:09 -0700 Mike Pavone Clear the low 2 bits of CD when a register is written to
Sun, 15 Sep 2013 23:40:18 -0700 Mike Pavone Don't allow register writes to regs above when in Mode 4
Sun, 15 Sep 2013 23:33:24 -0700 Mike Pavone Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
Sun, 15 Sep 2013 23:00:17 -0700 Mike Pavone Implement undocumented 8-bit VRAM read
Sun, 15 Sep 2013 22:43:01 -0700 Mike Pavone Fix VSRAM reads
Sun, 15 Sep 2013 22:20:43 -0700 Mike Pavone Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly