log

age author description
Tue, 27 Nov 2012 22:50:09 -0800 Mike Pavone Add Makefile
Tue, 27 Nov 2012 22:43:32 -0800 Mike Pavone Make x86 generator generic with respect to operand size for immediate parameters.
Tue, 27 Nov 2012 09:28:13 -0800 Mike Pavone x86 code gen, initial work on translator
Thu, 15 Nov 2012 22:15:43 -0800 Mike Pavone Improve disassembly. FIx some decoding bugs.
Thu, 15 Nov 2012 00:52:53 -0800 Mike Pavone Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Wed, 14 Nov 2012 23:04:55 -0800 Mike Pavone Implement OR_DIV_SBCD group in decoder
Wed, 14 Nov 2012 09:24:40 -0800 Mike Pavone Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Tue, 13 Nov 2012 18:26:43 -0800 Mike Pavone Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Fri, 09 Nov 2012 22:01:26 -0800 Mike Pavone Finish bit/movep/immediate group except for 68020 instructions
Tue, 06 Nov 2012 02:07:45 -0800 Mike Pavone merge
Tue, 06 Nov 2012 01:57:36 -0800 Mike Pavone Add some logic analyzer captures, a Python script for analyzing said captures and a higher level analysis of the output
Tue, 06 Nov 2012 02:04:42 -0800 Mike Pavone More bit and immediate instructions
Sun, 04 Nov 2012 23:43:03 -0800 Mike Pavone Add support for some bit instructions and a few others in the same "category"
Sat, 03 Nov 2012 22:15:55 -0700 Mike Pavone Finish mulu.w, muls.w and abcd parameter decoding
Sat, 03 Nov 2012 21:38:28 -0700 Mike Pavone Improve 68K instruction decoding. Add simple disassembler.