Tue, 01 Oct 2013 23:51:16 -0700 |
Mike Pavone |
Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button
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Wed, 18 Sep 2013 19:10:54 -0700 |
Mike Pavone |
Theoretically more correct timing of Z80 bus request
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Tue, 17 Sep 2013 19:10:00 -0700 |
Mike Pavone |
Set VBLANK flag in status register when display is disabled
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Tue, 17 Sep 2013 09:45:14 -0700 |
Mike Pavone |
Implement HV counter latch
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Tue, 17 Sep 2013 00:42:49 -0700 |
Mike Pavone |
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
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Tue, 17 Sep 2013 00:11:45 -0700 |
Mike Pavone |
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
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Mon, 16 Sep 2013 09:44:22 -0700 |
Mike Pavone |
Partial fix for DMA copy
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Sun, 15 Sep 2013 23:49:09 -0700 |
Mike Pavone |
Clear the low 2 bits of CD when a register is written to
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Sun, 15 Sep 2013 23:40:18 -0700 |
Mike Pavone |
Don't allow register writes to regs above when in Mode 4
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Sun, 15 Sep 2013 23:33:24 -0700 |
Mike Pavone |
Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
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Sun, 15 Sep 2013 23:00:17 -0700 |
Mike Pavone |
Implement undocumented 8-bit VRAM read
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Sun, 15 Sep 2013 22:43:01 -0700 |
Mike Pavone |
Fix VSRAM reads
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Sun, 15 Sep 2013 22:20:43 -0700 |
Mike Pavone |
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
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Fri, 13 Sep 2013 19:22:46 -0700 |
Mike Pavone |
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
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