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Wed, 27 Apr 2016 23:11:24 -0700
Michael Pavone
Implement privelege violation exceptions
Wed, 27 Apr 2016 21:39:17 -0700
Michael Pavone
Implemented IR and undefined bits of info word for address error exception frames
Wed, 27 Apr 2016 19:10:50 -0700
Michael Pavone
Fix changes made to get_instruction_start and map_native_address to cope with being able to translate at odd addresses.
Tue, 26 Apr 2016 23:13:37 -0700
Michael Pavone
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Tue, 26 Apr 2016 00:07:15 -0700
Michael Pavone
Implement illegal instruction trap
Sun, 24 Apr 2016 21:23:28 -0700
Michael Pavone
Fix interrupt latency from STOP instruction status reg changes. Fix modified code patching when non-standard aliases are used. This fixes the demo MDEM's First
Sun, 24 Apr 2016 14:30:15 -0700
Michael Pavone
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Sun, 24 Apr 2016 11:53:59 -0700
Michael Pavone
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
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