Wed, 27 Apr 2016 23:11:24 -0700 |
Michael Pavone |
Implement privelege violation exceptions
|
Wed, 27 Apr 2016 21:39:17 -0700 |
Michael Pavone |
Implemented IR and undefined bits of info word for address error exception frames
|
Wed, 27 Apr 2016 19:10:50 -0700 |
Michael Pavone |
Fix changes made to get_instruction_start and map_native_address to cope with being able to translate at odd addresses.
|
Tue, 26 Apr 2016 23:13:37 -0700 |
Michael Pavone |
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
|
Tue, 26 Apr 2016 00:07:15 -0700 |
Michael Pavone |
Implement illegal instruction trap
|
Sun, 24 Apr 2016 21:23:28 -0700 |
Michael Pavone |
Fix interrupt latency from STOP instruction status reg changes. Fix modified code patching when non-standard aliases are used. This fixes the demo MDEM's First
|
Sun, 24 Apr 2016 14:30:15 -0700 |
Michael Pavone |
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
|
Sun, 24 Apr 2016 11:53:59 -0700 |
Michael Pavone |
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
|
Sun, 24 Apr 2016 02:21:40 -0700 |
Michael Pavone |
Add a trivial get_open_bus_value() function to stateview so it compiles again.
|
Sun, 24 Apr 2016 02:19:48 -0700 |
Michael Pavone |
Half assed, prefetch based open bus value emulation. Gets BlastEm up to 119/122 in VDP FIFO Testing
|
Sun, 24 Apr 2016 01:24:38 -0700 |
Michael Pavone |
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
|
Sun, 24 Apr 2016 00:22:38 -0700 |
Michael Pavone |
Fix order of writes for move.l with a predec destination
|