Sat, 08 Dec 2012 16:09:43 -0800 |
Mike Pavone |
Partially fix BG plane B
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Sat, 08 Dec 2012 16:02:17 -0800 |
Mike Pavone |
Fix endianness of VSRAM when read from Genecyst save state
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Sat, 08 Dec 2012 11:59:50 -0800 |
Mike Pavone |
Sprites fixed, working on bg planes
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Sat, 08 Dec 2012 11:12:17 -0800 |
Mike Pavone |
Sprites somewhat less broken
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Sat, 08 Dec 2012 02:00:54 -0800 |
Mike Pavone |
Mostly broken VDP core and savestate viewer
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Tue, 04 Dec 2012 19:25:54 -0800 |
Mike Pavone |
Initial support for M68k reset vector, rather than starting at an arbitrary address
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Tue, 04 Dec 2012 19:13:12 -0800 |
Mike Pavone |
M68K to x86 translation works for a limited subset of instructions and addressing modes
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Tue, 27 Nov 2012 22:54:38 -0800 |
Mike Pavone |
Add asssembly runtime code stub
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Tue, 27 Nov 2012 22:50:09 -0800 |
Mike Pavone |
Add Makefile
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Tue, 27 Nov 2012 22:43:32 -0800 |
Mike Pavone |
Make x86 generator generic with respect to operand size for immediate parameters.
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Tue, 27 Nov 2012 09:28:13 -0800 |
Mike Pavone |
x86 code gen, initial work on translator
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Thu, 15 Nov 2012 22:15:43 -0800 |
Mike Pavone |
Improve disassembly. FIx some decoding bugs.
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Thu, 15 Nov 2012 00:52:53 -0800 |
Mike Pavone |
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
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Wed, 14 Nov 2012 23:04:55 -0800 |
Mike Pavone |
Implement OR_DIV_SBCD group in decoder
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Wed, 14 Nov 2012 09:24:40 -0800 |
Mike Pavone |
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
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