Mercurial > repos > blastem
changeset 162:eba78ad49a11
Implement more movem modes src
author | Mike Pavone <pavone@retrodev.com> |
---|---|
date | Sat, 05 Jan 2013 02:18:31 -0800 |
parents | 6748022656b7 |
children | 5559616e6bd8 |
files | m68k_to_x86.c |
diffstat | 1 files changed, 94 insertions(+), 0 deletions(-) [+] |
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--- a/m68k_to_x86.c Sat Jan 05 01:55:11 2013 -0800 +++ b/m68k_to_x86.c Sat Jan 05 02:18:31 2013 -0800 @@ -1152,6 +1152,100 @@ dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); } break; + case MODE_AREG_DISPLACE: + early_cycles += BUS; + reg = SCRATCH2; + if (opts->aregs[inst->dst.params.regs.pri] >= 0) { + dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); + } else { + dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); + } + dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); + break; + case MODE_AREG_INDEX_DISP8: + early_cycles += 6; + if (opts->aregs[inst->dst.params.regs.pri] >= 0) { + dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); + } else { + dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); + } + sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; + if (inst->dst.params.regs.sec & 1) { + if (inst->dst.params.regs.sec & 0x10) { + if (opts->aregs[sec_reg] >= 0) { + dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); + } else { + dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); + } + } else { + if (opts->dregs[sec_reg] >= 0) { + dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); + } else { + dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); + } + } + } else { + if (inst->dst.params.regs.sec & 0x10) { + if (opts->aregs[sec_reg] >= 0) { + dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); + } else { + dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); + } + } else { + if (opts->dregs[sec_reg] >= 0) { + dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); + } else { + dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); + } + } + dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); + } + if (inst->dst.params.regs.displacement) { + dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); + } + break; + case MODE_PC_DISPLACE: + early_cycles += BUS; + dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D); + break; + case MODE_PC_INDEX_DISP8: + early_cycles += 6; + dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); + sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; + if (inst->dst.params.regs.sec & 1) { + if (inst->dst.params.regs.sec & 0x10) { + if (opts->aregs[sec_reg] >= 0) { + dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); + } else { + dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); + } + } else { + if (opts->dregs[sec_reg] >= 0) { + dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); + } else { + dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); + } + } + } else { + if (inst->dst.params.regs.sec & 0x10) { + if (opts->aregs[sec_reg] >= 0) { + dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); + } else { + dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); + } + } else { + if (opts->dregs[sec_reg] >= 0) { + dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); + } else { + dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); + } + } + dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); + } + if (inst->dst.params.regs.displacement) { + dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); + } + break; case MODE_ABSOLUTE: early_cycles += 4; case MODE_ABSOLUTE_SHORT: