Mercurial > repos > blastem
changeset 2426:cde4ea2b4929
Clear DSR in certain gate array writes. Fixes issue in Penn & Teller's Smoke and Mirrors
author | Michael Pavone <pavone@retrodev.com> |
---|---|
date | Thu, 25 Jan 2024 21:54:04 -0800 |
parents | 794ba17f0716 |
children | 8b948cf23557 |
files | segacd.c |
diffstat | 1 files changed, 9 insertions(+), 0 deletions(-) [+] |
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--- a/segacd.c Wed Jan 24 20:18:17 2024 -0800 +++ b/segacd.c Thu Jan 25 21:54:04 2024 -0800 @@ -856,11 +856,18 @@ } cd->gate_array[GA_CDC_DMA_ADDR] = 0; cd->cdc_dst_low = 0; + //TODO: Confirm if DSR is cleared here on hardware + cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR; break; } case GA_CDC_REG_DATA: cdd_run(cd, m68k->current_cycle); printf("CDC write %X: %X @ %u\n", cd->cdc.ar, value, m68k->current_cycle); + if (cd->cdc.ar == 6) { + cd->cdc_dst_low = 0; + //TODO: Confirm if DSR is cleared here on hardware + cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR; + } lc8951_reg_write(&cd->cdc, value); calculate_target_cycle(m68k); break; @@ -872,6 +879,8 @@ cdd_run(cd, m68k->current_cycle); cd->gate_array[reg] = value; cd->cdc_dst_low = 0; + //TODO: Confirm if DSR is cleared here on hardware + cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR; break; case GA_STOP_WATCH: //docs say you should only write zero to reset