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changeset 2502:ad50530a7c27

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Partially functional asr/asl implementations in new 68K core
author Michael Pavone <pavone@retrodev.com>
date Tue, 16 Jul 2024 20:21:08 -0700
parents 6cd5a1d76e34
children fa49e06d8c92
files cpu_dsl.py m68k.cpu
diffstat 2 files changed, 172 insertions(+), 8 deletions(-) [+]
line wrap: on
line diff
--- a/cpu_dsl.py	Wed May 01 01:19:30 2024 -0700
+++ b/cpu_dsl.py	Tue Jul 16 20:21:08 2024 -0700
@@ -502,8 +502,7 @@
 					if type(prog.lastB) is int:
 						resultBit = prog.lastB - 1
 					else:
-						#FIXME!!!!!
-						resultBit = 0
+						resultBit = f'({prog.lastB} - 1)'
 					myRes = prog.lastA
 				elif prog.lastOp.op == 'neg':
 					if prog.carryFlowDst:
@@ -554,10 +553,17 @@
 			else:
 				reg = prog.resolveParam(storage, None, {})
 				maxBit = prog.paramSize(storage) - 1
-				if resultBit > maxBit:
-					output.append('\n\t{reg} = {res} >> {shift} & {mask}U;'.format(reg=reg, res=myRes, shift = resultBit - maxBit, mask = 1 << maxBit))
+				if type(resultBit) is int:
+					mask = f'{1 << resultBit}U'
 				else:
-					output.append('\n\t{reg} = {res} & {mask}U;'.format(reg=reg, res=myRes, mask = 1 << resultBit))
+					mask = f'(1 << {resultBit})'
+				if not type(resultBit) is int:
+					output.append(f'\n\t{reg} = !!({myRes} & {mask});')
+				elif resultBit > maxBit:
+					mask = f'{1 << maxBit}U'
+					output.append('\n\t{reg} = {res} >> {shift} & {mask};'.format(reg=reg, res=myRes, shift = resultBit - maxBit, mask = mask))
+				else:
+					output.append('\n\t{reg} = {res} & {mask};'.format(reg=reg, res=myRes, mask = mask))
 		elif calc == 'zero':
 			if prog.carryFlowDst:
 				realSize = prog.getLastSize()
@@ -694,14 +700,41 @@
 			if calc == 'carry':
 				needsCarry = True
 	decl = ''
-	size = prog.paramSize(rawParams[2])
+	needsSizeAdjust = False
+	destSize = prog.paramSize(rawParams[2])
+	if len(params) > 3:
+		size = params[3]
+		if size == 0:
+			size = 8
+		elif size == 1:
+			size = 16
+		else:
+			size = 32
+		prog.lastSize = size
+		if destSize > size:
+			needsSizeAdjust = True
+			prog.sizeAdjust = size
+	else:
+		size = destSize
+	mask = 1 << (size - 1)
 	if needsCarry:
-		decl,name = prog.getTemp(size * 2)
+		decl,name = prog.getTemp(size)
 		dst = prog.carryFlowDst = name
 		prog.lastA = params[0]
+		prog.lastB = params[1]
+		if needsSizeAdjust:
+			sizeMask = (1 << size) - 1
+			return decl + '\n\t{name} = (({a} & {sizeMask}) >> ({b} & {sizeMask})) | ({a} & {mask} ? 0xFFFFFFFFU << ({size} - ({b} & {sizeMask})) : 0);'.format(
+				name = name, a = params[0], b = params[1], dst = dst, mask = mask, size=size, sizeMask=sizeMask)
+	elif needsSizeAdjust:
+		decl,name = prog.getTemp(size)
+		sizeMask = (1 << size) - 1
+		return decl + ('\n\t{name} = (({a} & {sizeMask}) >> ({b} & {sizeMask})) | ({a} & {mask} ? 0xFFFFFFFFU << ({size} - ({b} & {sizeMask})) : 0);' +
+			'\n\t{dst} = ({dst} & ~{sizeMask}) | {name};').format(
+			name = name, a = params[0], b = params[1], dst = dst, mask = mask, size=size, sizeMask=sizeMask)
 	else:
 		dst = params[2]
-	mask = 1 << (size - 1)
+	
 	return decl + '\n\t{dst} = ({a} >> {b}) | ({a} & {mask} ? 0xFFFFFFFFU << ({size} - {b}) : 0);'.format(
 		a = params[0], b = params[1], dst = dst, mask = mask, size=size)
 	
--- a/m68k.cpu	Wed May 01 01:19:30 2024 -0700
+++ b/m68k.cpu	Tue Jul 16 20:21:08 2024 -0700
@@ -1021,6 +1021,82 @@
 	update_flags XNZV0C
 	m68k_save_dst 0
 	m68k_prefetch
+
+1110CCC0ZZ000RRR asri
+	invalid Z 3
+	switch C
+	case 0
+		meta shift 8
+	default
+		meta shift C
+	end
+	asr dregs.R shift dregs.R Z
+	update_flags XNZV0C
+	local cyc 32
+	cyc = shift + shift
+	switch Z
+	case 2
+		cyc += 4
+	default
+		cyc += 2
+	end
+	cycles cyc
+	#TODO: should this happen before or after the majority of the shift?
+	m68k_prefetch
+	
+1110CCC0ZZ100RRR asr_dn
+	invalid Z 3
+	local shift 32
+	local shift_cycles 32
+	and dregs.C 63 shift
+	shift_cycles = shift
+	if shift = 0
+		cmp 0 dregs.R Z
+		update_flags NZV0C0
+	else
+		switch Z
+		case 0
+			if shift >=U 9
+				shift = 8
+			end
+		case 1
+			if shift >=U 17
+				shift = 16
+			end
+		case 2
+			if shift >=U 33
+				shift = 32
+			end
+		end
+		asr dregs.R shift dregs.R Z
+		update_flags XNZV0C
+	end
+	shift_cycles += shift_cycles
+	switch Z
+	case 2
+		shift_cycles += 4
+	default
+		shift_cycles += 2
+	end
+	cycles shift_cycles
+	#TODO: should this happen before or after the majority of the shift?
+	m68k_prefetch
+
+1110000011MMMRRR asr_ea
+	invalid M 0
+	invalid M 1
+	invalid M 7 R 2
+	invalid M 7 R 3
+	invalid M 7 R 4
+	invalid M 7 R 5
+	invalid M 7 R 6
+	invalid M 7 R 7
+	
+	m68k_fetch_dst_ea M R 0
+	asr dst 1 dst
+	update_flags XNZV0C
+	m68k_save_dst 0
+	m68k_prefetch
 	
 1110CCC1ZZ001RRR lsli
 	invalid Z 3
@@ -1077,6 +1153,61 @@
 	m68k_save_dst 0
 	m68k_prefetch
 
+1110CCC1ZZ000RRR asli
+	invalid Z 3
+	switch C
+	case 0
+		meta shift 8
+	default
+		meta shift C
+	end
+	lsl dregs.R shift dregs.R Z
+	update_flags XNZV0C
+	local cyc 32
+	cyc = shift + shift
+	switch Z
+	case 2
+		cyc += 4
+	default
+		cyc += 2
+	end
+	cycles cyc
+	#TODO: should this happen before or after the majority of the shift?
+	m68k_prefetch
+	
+1110CCC1ZZ100RRR asl_dn
+	invalid Z 3
+	local shift 8
+	and dregs.C 63 shift
+	lsl dregs.R shift dregs.R Z
+	update_flags XNZV0C
+	add shift shift shift
+	switch Z
+	case 2
+		add 4 shift shift
+	default
+		add 2 shift shift
+	end
+	cycles shift
+	#TODO: should this happen before or after the majority of the shift?
+	m68k_prefetch
+
+1110000111MMMRRR asl_ea
+	invalid M 0
+	invalid M 1
+	invalid M 7 R 2
+	invalid M 7 R 3
+	invalid M 7 R 4
+	invalid M 7 R 5
+	invalid M 7 R 6
+	invalid M 7 R 7
+	
+	m68k_fetch_dst_ea M R 0
+	lsl dst 1 dst
+	update_flags XNZV0C
+	m68k_save_dst 0
+	m68k_prefetch
+
 00ZZRRRMMMEEESSS move
 	invalid Z 0
 	invalid M 1