Mercurial > repos > blastem
changeset 217:acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
author | Mike Pavone <pavone@retrodev.com> |
---|---|
date | Sat, 20 Apr 2013 00:29:14 -0700 |
parents | 0b5ec22dcda2 |
children | 1abf8e967b33 |
files | comparetests.py gentests.py testcases.txt |
diffstat | 3 files changed, 66 insertions(+), 22 deletions(-) [+] |
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--- a/comparetests.py Fri Apr 19 21:36:54 2013 -0700 +++ b/comparetests.py Sat Apr 20 00:29:14 2013 -0700 @@ -5,10 +5,10 @@ for path in glob('generated_tests/*.bin'): try: - b = subprocess.check_output(['./blastem', path]) + b = subprocess.check_output(['./blastem', path, '-v']) try: m = subprocess.check_output(['musashi/mustrans', path]) - _,_,b = b.partition('\n') + #_,_,b = b.partition('\n') if b != m: print '-----------------------------' print 'Mismatch in ' + path
--- a/gentests.py Fri Apr 19 21:36:54 2013 -0700 +++ b/gentests.py Sat Apr 20 00:29:14 2013 -0700 @@ -106,29 +106,41 @@ already['label'] = num address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp) + ' + ' + str(index) else: - if str(self.base) in already: - if not valid_ram_address(already[str(self.base)]): - del already[str(self.base)] - self.write_init(outfile, size, already) - return + if self.base == self.index: + if str(self.base) in already: + if not valid_ram_address(already[str(self.base)]*2): + del already[str(self.base)] + self.write_init(outfile, size, already) + return + else: + base = index = already[str(self.base)] else: - base = already[str(self.base)] + base = index = already[str(self.base)] = random_ram_address()/2 + outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n') else: - base = already[str(self.base)] = random_ram_address() - outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n') - if str(self.index) in already: - index = already[str(self.index)] - if self.index_size == 'w': - index = index & 0xFFFF - #sign extend index - if index & 0x8000: - index -= 65536 - if not valid_ram_address(base + index): + if str(self.base) in already: + if not valid_ram_address(already[str(self.base)]): + del already[str(self.base)] + self.write_init(outfile, size, already) + return + else: + base = already[str(self.base)] + else: + base = already[str(self.base)] = random_ram_address() + outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n') + if str(self.index) in already: + index = already[str(self.index)] + if self.index_size == 'w': + index = index & 0xFFFF + #sign extend index + if index & 0x8000: + index -= 65536 + if not valid_ram_address(base + index): + index = already[str(self.index)] = randint(-64, 63) + outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n') + else: index = already[str(self.index)] = randint(-64, 63) outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n') - else: - index = already[str(self.index)] = randint(-64, 63) - outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n') address = base + index + self.disp if (address & 0xFFFFFF) < 0xE00000: if (address & 0xFFFFFF) < 128: @@ -366,6 +378,9 @@ inner = mode[2:-1] start,sep,end = inner.partition('-') return [Immediate(num) for num in range(int(start), int(end))] + else: + print "Don't know what to do with source type", mode + return None class Inst2Op(object): def __init__(self, name, size, src, dst): @@ -387,7 +402,13 @@ def save_result(self, reg, always): if always or type(self.dst) != Register: - return 'move.' + self.size + ' ' + str(self.dst) + ', ' + str(reg) + if type(self.dst) == Decrement: + src = Increment(self.dst.reg) + elif type(self.dst) == Increment: + src = Decrement(self.dst.reg) + else: + src = self.dst + return 'move.' + self.size + ' ' + str(src) + ', ' + str(reg) else: return ''
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/testcases.txt Sat Apr 20 00:29:14 2013 -0700 @@ -0,0 +1,23 @@ +Name Sizes Src Modes Dst Modes +add bwl d;a;(a);(a)+;-(a);(n,a);(n,a,x);(n).w;(n).l;#n;(n,pc);(n,pc,x) d +add bwl d (a);(a)+;-(a);(n,a);(n,a,x);(n).w;(n).l +adda wl d;a;(a);(a)+;-(a);(n,a);(n,a,x);(n).w;(n).l;#n;(n,pc);(n,pc,x) a +addi bwl #n d;(a);(a)+;-(a);(n,a);(n,a,x);(n).w;(n).l +addq bwl #(1-8) d;a;(a);(a)+;-(a);(n,a);(n,a,x);(n).w;(n).l +addx bwl d d +addx bwl -(a) -(a) +and bwl d;(a);(a)+;-(a);(n,a);(n,a,x);(n).w;(n).l;#n;(n,pc);(n,pc,x) d +and bwl d (a);(a)+;-(a);(n,a);(n,a,x);(n).w;(n).l +andi bwl #n d;(a);(a)+;-(a);(n,a);(n,a,x);(n).w;(n).l +asl bwl d;#(1-8) d +asr bwl d;#(1-8) d +lsl bwl d;#(1-8) d +lsr bwl d;#(1-8) d +sub bwl d;a;(a);(a)+;-(a);(n,a);(n,a,x);(n).w;(n).l;#n;(n,pc);(n,pc,x) d +sub bwl d (a);(a)+;-(a);(n,a);(n,a,x);(n).w;(n).l +suba wl d;a;(a);(a)+;-(a);(n,a);(n,a,x);(n).w;(n).l;#n;(n,pc);(n,pc,x) a +subi bwl #n d;(a);(a)+;-(a);(n,a);(n,a,x);(n).w;(n).l +subq bwl #(1-8) d;a;(a);(a)+;-(a);(n,a);(n,a,x);(n).w;(n).l +subx bwl d d +subx bwl -(a) -(a) +