Mercurial > repos > blastem
changeset 2101:17ecd28ddc8a
Fix handling of address error for 32-bit accesses
author | Michael Pavone <pavone@retrodev.com> |
---|---|
date | Wed, 09 Feb 2022 23:39:33 -0800 |
parents | 539450d905b3 |
children | f3fb7e2c727a |
files | m68k_core_x86.c |
diffstat | 1 files changed, 12 insertions(+), 0 deletions(-) [+] |
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--- a/m68k_core_x86.c Wed Feb 09 23:39:03 2022 -0800 +++ b/m68k_core_x86.c Wed Feb 09 23:39:33 2022 -0800 @@ -2738,6 +2738,10 @@ opts->write_8 = gen_mem_fun(&opts->gen, memmap, num_chunks, WRITE_8, NULL); opts->read_32 = code->cur; + if (opts->gen.align_error_mask) { + test_ir(code, opts->gen.align_error_mask, opts->gen.scratch1, SZ_D); + jcc(code, CC_NZ, opts->gen.handle_align_error_read); + } push_r(code, opts->gen.scratch1); call(code, opts->read_16); mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_W); @@ -2752,6 +2756,10 @@ retn(code); opts->write_32_lowfirst = code->cur; + if (opts->gen.align_error_mask) { + test_ir(code, opts->gen.align_error_mask, opts->gen.scratch2, SZ_D); + jcc(code, CC_NZ, opts->gen.handle_align_error_write); + } push_r(code, opts->gen.scratch2); push_r(code, opts->gen.scratch1); add_ir(code, 2, opts->gen.scratch2, SZ_D); @@ -2762,6 +2770,10 @@ jmp(code, opts->write_16); opts->write_32_highfirst = code->cur; + if (opts->gen.align_error_mask) { + test_ir(code, opts->gen.align_error_mask, opts->gen.scratch2, SZ_D); + jcc(code, CC_NZ, opts->gen.handle_align_error_write); + } push_r(code, opts->gen.scratch1); push_r(code, opts->gen.scratch2); shr_ir(code, 16, opts->gen.scratch1, SZ_D);