log trans.c @ 2496:187bc857a76a default tip

age author description
Thu, 15 Feb 2024 21:49:17 -0800 Michael Pavone Fix some issues in new 68K core and add implementations of negx and clr instructions
Tue, 13 Feb 2024 21:18:47 -0800 Michael Pavone Get 68K test harness compiling again
Thu, 05 Aug 2021 09:29:33 -0700 Michael Pavone Merge from default mame_interp
Sat, 13 Jun 2020 00:37:22 -0700 Michael Pavone Somewhat buggy implementations of shift instructions in new 68K core
Fri, 12 Jun 2020 23:54:22 -0700 Michael Pavone Fix 68k test harness target, add cycle count to output and add a cycle limit
Sat, 18 Apr 2020 11:42:53 -0700 Michael Pavone Merge from default mame_interp
Thu, 18 Apr 2019 19:47:50 -0700 Michael Pavone WIP new 68K core using CPU DSL
Sat, 30 Dec 2017 18:27:06 -0800 Michael Pavone Added MAME Z80 core, re-enabled 68K tracing in Musashi core, disabled a bunch of code gen stuff when using interpreters from MAME mame_interp
Tue, 28 Mar 2017 09:39:54 -0700 Michael Pavone Fix exit trace mode edge case. Call do_sync if trace mode bit is changed in eori sr
Tue, 28 Mar 2017 00:13:35 -0700 Michael Pavone Implemented M68K trace mode. Some edge cases/SR update paths still need work
Thu, 06 Oct 2016 09:34:31 -0700 Michael Pavone Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
Wed, 28 Oct 2015 19:40:01 -0700 Michael Pavone Get trans program compiling again
Sat, 16 May 2015 22:42:26 -0700 Michael Pavone Fix trans so it compiles again
Mon, 03 Mar 2014 21:08:43 -0800 Michael Pavone Make some small changes in trans so that it is more likely to produce the same output as mustrans when given misbehaving programs. Add lea to testcases.txt. Improve the output of comparetest.py so that known issues can easily be separated from new ones.
Sun, 02 Mar 2014 16:34:29 -0800 Michael Pavone Initial stab at separating the generic parts of the 68K core from the host-cpu specific parts.