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log vdp.h @ 489:e97b80e3bd76 opengl

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age author description
Tue, 17 Sep 2013 09:45:14 -0700 Mike Pavone Implement HV counter latch
Tue, 17 Sep 2013 00:11:45 -0700 Mike Pavone Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Sun, 15 Sep 2013 22:20:43 -0700 Mike Pavone Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
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