Sun, 15 Jan 2017 15:07:24 -0800 |
Michael Pavone |
Initial work on emulating top and bottom border area
|
Thu, 05 Jan 2017 00:36:23 -0800 |
Michael Pavone |
Implemented Mode 4 H conter latching
|
Wed, 04 Jan 2017 20:43:22 -0800 |
Michael Pavone |
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
|
Sun, 01 Jan 2017 21:06:32 -0800 |
Michael Pavone |
Update Mode 4 rendering to match logic analyzer captures
|
Tue, 27 Dec 2016 11:31:17 -0800 |
Michael Pavone |
Somewhat broken implementation of Mode 4
|
Thu, 22 Dec 2016 19:51:25 -0800 |
Michael Pavone |
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
|
Mon, 28 Nov 2016 22:45:46 -0800 |
Michael Pavone |
Clean up symbol visiblity and delete a ltitle bit of dead code
|
Mon, 22 Aug 2016 09:46:18 -0700 |
Michael Pavone |
Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
|
Mon, 02 May 2016 23:08:20 -0700 |
Michael Pavone |
Fix GST savestate loading to deal with SAT cache to fix sprite corruption on savestate load. Clear out Z80 native_pc so the Z80 state does not get hosed when loading a savestate while the emulator is already running
|
Sat, 30 Apr 2016 15:31:48 -0700 |
Michael Pavone |
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
|
Sun, 24 Apr 2016 01:24:38 -0700 |
Michael Pavone |
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
|
Tue, 12 Apr 2016 21:38:24 -0700 |
Michael Pavone |
Remove the int number argument to vdp_int_ack since it is no longer used
|
Thu, 28 Jan 2016 09:10:14 -0800 |
Michael Pavone |
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
|
Fri, 13 Nov 2015 22:56:59 -0800 |
Michael Pavone |
Selecting a second game from the menu now works
|
Thu, 21 May 2015 00:55:46 -0700 |
Michael Pavone |
Restore the other 2 debug display modes
|
Tue, 19 May 2015 23:23:53 -0700 |
Michael Pavone |
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
|
Sat, 16 May 2015 23:04:57 -0700 |
Michael Pavone |
First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it
|
Mon, 11 May 2015 00:28:47 -0700 |
Michael Pavone |
Sync fixes and logging to fix more sync issues
|
Sun, 04 Jan 2015 23:05:37 -0800 |
Michael Pavone |
Some small synchronization improvements that do not seem to fix anything
|
Wed, 18 Jun 2014 16:30:19 -0700 |
Michael Pavone |
Fix most of the breakage caused by the vcounter/hcounter changes
|
Tue, 17 Jun 2014 19:01:01 -0700 |
Michael Pavone |
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
|
Mon, 07 Oct 2013 10:02:08 -0700 |
Mike Pavone |
Initial implementation of sprite overflow and sprite collision status register flags
|
Tue, 17 Sep 2013 09:45:14 -0700 |
Mike Pavone |
Implement HV counter latch
|
Tue, 17 Sep 2013 00:11:45 -0700 |
Mike Pavone |
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
|
Sun, 15 Sep 2013 22:20:43 -0700 |
Mike Pavone |
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
|
Fri, 13 Sep 2013 19:22:46 -0700 |
Mike Pavone |
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
|
Tue, 10 Sep 2013 23:31:08 -0700 |
Mike Pavone |
Added copyright notice to source files and added GPL license text in COPYING
|
Tue, 10 Sep 2013 00:29:46 -0700 |
Mike Pavone |
Implement FIFO latency and improve DMA accuracy
|