log cpu_dsl.py @ 2500:d44fe974fb85

age author description
Tue, 30 Apr 2024 22:32:08 -0700 Michael Pavone Get blastem compiling with new 68K core
Tue, 30 Apr 2024 00:02:14 -0700 Michael Pavone Make some progress on compiling full emulator with new 68K core
Mon, 29 Apr 2024 22:57:33 -0700 Michael Pavone Fix constant propagation for sext instruction
Thu, 07 Mar 2024 00:53:11 -0800 Michael Pavone Implement lea and pea in new 68K core
Sat, 24 Feb 2024 22:54:36 -0800 Michael Pavone Implement ext instruction in new 68K core
Fri, 23 Feb 2024 23:09:07 -0800 Michael Pavone Fix carry flag calculation for neg instruction in CPU DSL
Mon, 19 Feb 2024 18:14:12 -0800 Michael Pavone Allow more if statements to be constant folded in CPU DSL
Mon, 19 Feb 2024 17:55:45 -0800 Michael Pavone Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands
Thu, 15 Feb 2024 21:49:17 -0800 Michael Pavone Fix some issues in new 68K core and add implementations of negx and clr instructions
Mon, 12 Feb 2024 07:42:32 -0800 Michael Pavone Sugar for unary operators in CPU DSL
Sun, 11 Feb 2024 20:41:28 -0800 Michael Pavone Sugar for some basic conditionals in CPU DSL
Sun, 11 Feb 2024 20:15:00 -0800 Michael Pavone Sugar for binary operators in CPU DSL
Sun, 11 Feb 2024 17:26:52 -0800 Michael Pavone Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Sat, 13 Jun 2020 00:37:22 -0700 Michael Pavone Somewhat buggy implementations of shift instructions in new 68K core
Thu, 23 Apr 2020 20:57:14 -0700 Michael Pavone Fix autogenerated temp variables in interrupt subroutine in CPU DSL
Sat, 21 Sep 2019 10:48:10 -0700 Michael Pavone Implement interrupts in call dispatch mode in CPU DSL