Tue, 17 Sep 2013 09:45:14 -0700 |
Mike Pavone |
Implement HV counter latch
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Tue, 17 Sep 2013 00:11:45 -0700 |
Mike Pavone |
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
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Sun, 15 Sep 2013 22:20:43 -0700 |
Mike Pavone |
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
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Fri, 13 Sep 2013 19:22:46 -0700 |
Mike Pavone |
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
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Tue, 10 Sep 2013 23:31:08 -0700 |
Mike Pavone |
Added copyright notice to source files and added GPL license text in COPYING
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Tue, 10 Sep 2013 00:29:46 -0700 |
Mike Pavone |
Implement FIFO latency and improve DMA accuracy
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Fri, 26 Jul 2013 19:55:04 -0700 |
Mike Pavone |
Added support for saving savestates. Added gst savestate format test harness
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Mon, 15 Jul 2013 23:07:45 -0700 |
Mike Pavone |
Restore one of the VDP debugging modes
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Fri, 12 Jul 2013 19:11:55 -0700 |
Mike Pavone |
Implement the scroll ring buffer properly without memcpy
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Sun, 30 Jun 2013 11:45:58 -0700 |
Mike Pavone |
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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Sat, 29 Jun 2013 17:15:08 -0700 |
Mike Pavone |
Add support for loading GST format savestates
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Sat, 22 Jun 2013 21:19:43 -0700 |
Mike Pavone |
Initial work on interlace
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Wed, 15 May 2013 22:37:04 -0700 |
Mike Pavone |
Fix background color regsiter number
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Tue, 14 May 2013 00:40:10 -0700 |
Mike Pavone |
Update Z80 vint timing
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