log genesis.c @ 1907:b021ca0bc375

age author description
Wed, 25 Mar 2020 22:59:59 -0700 Michael Pavone Some partial work on TMSS registers, more accurate open bus locations and implement machine freezes for unmapped areas in the IO region
Thu, 27 Feb 2020 18:38:15 -0800 Michael Pavone Make VDP VSRAM capacity respect model selection
Wed, 26 Feb 2020 22:40:37 -0800 Michael Pavone Implement selectable YM2612/YM3834 invalid status port behavior
Mon, 24 Feb 2020 20:06:29 -0800 Michael Pavone Fix YM2612 busy flag timing
Sun, 16 Feb 2020 10:46:35 -0800 Michael Pavone Set version reg and TAS behavior based on model config
Sat, 21 Sep 2019 20:26:12 -0700 Michael Pavone Report more accurate frame and sample rates to frontend in libretro target
Mon, 19 Aug 2019 19:15:52 -0700 Michael Pavone Only do full sync on VDP data port reads instead of all VDP port reads, provides a perf bump for games that busy wait on the status or HV registers