| Wed, 25 Mar 2020 22:59:59 -0700 |
Michael Pavone |
Some partial work on TMSS registers, more accurate open bus locations and implement machine freezes for unmapped areas in the IO region
|
| Thu, 27 Feb 2020 18:38:15 -0800 |
Michael Pavone |
Make VDP VSRAM capacity respect model selection
|
| Wed, 26 Feb 2020 22:40:37 -0800 |
Michael Pavone |
Implement selectable YM2612/YM3834 invalid status port behavior
|
| Mon, 24 Feb 2020 20:06:29 -0800 |
Michael Pavone |
Fix YM2612 busy flag timing
|
| Sun, 16 Feb 2020 10:46:35 -0800 |
Michael Pavone |
Set version reg and TAS behavior based on model config
|
| Sat, 21 Sep 2019 20:26:12 -0700 |
Michael Pavone |
Report more accurate frame and sample rates to frontend in libretro target
|
| Mon, 19 Aug 2019 19:15:52 -0700 |
Michael Pavone |
Only do full sync on VDP data port reads instead of all VDP port reads, provides a perf bump for games that busy wait on the status or HV registers
|
| Mon, 24 Jun 2019 23:47:16 -0700 |
Michael Pavone |
Fix accuracy bugs used by Novedicus to detect BlastEm/Exodus
|
| Tue, 23 Apr 2019 23:31:34 -0700 |
Michael Pavone |
Don't print out a message when saving a state to the serialization pseudo-slot
|
| Tue, 23 Apr 2019 18:37:08 -0700 |
Michael Pavone |
16-bit wide save RAM is stored in memory byteswapped for performance reasons, but saving it to disc that way isn't great. Swap before save/after load to fix
|
| Sun, 14 Apr 2019 23:38:02 -0700 |
Michael Pavone |
Merge from default
mame_interp
|
| Sun, 24 Mar 2019 19:59:41 -0700 |
Michael Pavone |
Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
|
| Sat, 23 Mar 2019 17:18:10 -0700 |
Michael Pavone |
Configurable gain for overall output and individual components
|
| Wed, 13 Mar 2019 20:34:24 -0700 |
Michael Pavone |
Make get_open_bus_value work right with Musashi
mame_interp
|
