log m68k_core.h @ 2351:8f3cfb77f1e3

age author description
Wed, 18 Oct 2023 23:26:51 -0700 Michael Pavone Bump up 68K stack storage as old value was insufficient in some cases
Mon, 16 Oct 2023 23:30:04 -0700 Michael Pavone Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Sat, 07 Oct 2023 18:04:35 -0700 Michael Pavone Fix some issues identified by asan/ubsan
Tue, 30 Aug 2022 18:42:45 -0700 Michael Pavone Add disassemble command to debugger
Thu, 17 Mar 2022 22:41:42 -0700 Michael Pavone Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Tue, 18 Jan 2022 00:03:50 -0800 Michael Pavone Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM segacd
Thu, 05 Aug 2021 09:29:33 -0700 Michael Pavone Merge from default mame_interp
Sun, 21 Feb 2021 14:35:16 -0800 Michael Pavone Implement TMSS ROM and cart mapping register
Sat, 18 Apr 2020 11:42:53 -0700 Michael Pavone Merge from default mame_interp
Tue, 12 Mar 2019 21:58:53 -0700 Michael Pavone Wrote a version of m68k_invalidate_code_range for interpreter build so that MMAP_PTR_IDX regions can safely get "fast" pointers mame_interp
Sat, 30 Dec 2017 18:27:06 -0800 Michael Pavone Added MAME Z80 core, re-enabled 68K tracing in Musashi core, disabled a bunch of code gen stuff when using interpreters from MAME mame_interp
Sun, 06 Aug 2017 00:06:36 -0700 Michael Pavone WIP - New savestate format
Fri, 19 May 2017 20:27:35 -0700 Michael Pavone Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
Mon, 24 Apr 2017 20:49:31 -0700 Michael Pavone Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
Tue, 28 Mar 2017 00:13:35 -0700 Michael Pavone Implemented M68K trace mode. Some edge cases/SR update paths still need work