log cpu_dsl.py @ 1742:6290c88949bd

age author description
Mon, 04 Feb 2019 23:46:35 -0800 Michael Pavone Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Mon, 04 Feb 2019 22:20:51 -0800 Michael Pavone Implement DD/FD prefixes for instructions that don't reference HL
Mon, 04 Feb 2019 21:43:43 -0800 Michael Pavone Fixed some issues involving conditional execution and temporaries/constant folding
Sun, 03 Feb 2019 11:05:40 -0800 Michael Pavone Get new Z80 core running in CPM harness
Sun, 03 Feb 2019 10:40:41 -0800 Michael Pavone Implemented the rest of the block move instructions in new Z80 core
Sat, 02 Feb 2019 23:02:19 -0800 Michael Pavone Implemented LDI in new Z80 core
Sat, 02 Feb 2019 15:35:15 -0800 Michael Pavone Implemented RES instruction in new Z80 core
Fri, 01 Feb 2019 22:16:56 -0800 Michael Pavone Miscellaneous small fixes to new Z80 core
Thu, 31 Jan 2019 23:33:36 -0800 Michael Pavone Implemented shift instructions in new Z80 core
Thu, 31 Jan 2019 23:03:51 -0800 Michael Pavone Implemented the rest of the rotate instructions in new Z80 core
Thu, 31 Jan 2019 22:41:37 -0800 Michael Pavone Implementation of some of the rotate instructions in new Z80 core
Wed, 30 Jan 2019 21:47:35 -0800 Michael Pavone Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Wed, 30 Jan 2019 09:32:01 -0800 Michael Pavone Better error reporting when an instruction is given an insufficient number of parameters
Tue, 29 Jan 2019 23:56:48 -0800 Michael Pavone Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Tue, 29 Jan 2019 22:16:57 -0800 Michael Pavone Implement parity flag calculation type