log cpu_dsl.py @ 2443:461fffc226e0

age author description
Mon, 12 Feb 2024 07:42:32 -0800 Michael Pavone Sugar for unary operators in CPU DSL
Sun, 11 Feb 2024 20:41:28 -0800 Michael Pavone Sugar for some basic conditionals in CPU DSL
Sun, 11 Feb 2024 20:15:00 -0800 Michael Pavone Sugar for binary operators in CPU DSL
Sun, 11 Feb 2024 17:26:52 -0800 Michael Pavone Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it
Sat, 13 Jun 2020 00:37:22 -0700 Michael Pavone Somewhat buggy implementations of shift instructions in new 68K core
Thu, 23 Apr 2020 20:57:14 -0700 Michael Pavone Fix autogenerated temp variables in interrupt subroutine in CPU DSL
Sat, 21 Sep 2019 10:48:10 -0700 Michael Pavone Implement interrupts in call dispatch mode in CPU DSL
Thu, 18 Apr 2019 19:47:50 -0700 Michael Pavone WIP new 68K core using CPU DSL
Wed, 20 Feb 2019 00:34:52 -0800 Michael Pavone Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL
Tue, 19 Feb 2019 22:51:33 -0800 Michael Pavone Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Fri, 15 Feb 2019 23:58:34 -0800 Michael Pavone Basic support for string operands in CPU DSL
Tue, 12 Feb 2019 09:58:04 -0800 Michael Pavone Integration of new Z80 core is sort of working now