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log vdp.h @ 478:
2e4a4188cfb0
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Tue, 17 Sep 2013 00:11:45 -0700
Mike Pavone
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Sun, 15 Sep 2013 22:20:43 -0700
Mike Pavone
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Fri, 13 Sep 2013 19:22:46 -0700
Mike Pavone
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Tue, 10 Sep 2013 23:31:08 -0700
Mike Pavone
Added copyright notice to source files and added GPL license text in COPYING
Tue, 10 Sep 2013 00:29:46 -0700
Mike Pavone
Implement FIFO latency and improve DMA accuracy
Fri, 26 Jul 2013 19:55:04 -0700
Mike Pavone
Added support for saving savestates. Added gst savestate format test harness
Mon, 15 Jul 2013 23:07:45 -0700
Mike Pavone
Restore one of the VDP debugging modes
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