Mercurial > repos > blastem
graph
-
Fix timing for branch not taken case in the M68K BCC intructionWed, 26 Apr 2017 21:55:12 -0700, by Michael Pavone
-
Add 128K VRAM bit to VDP register print in debuggerWed, 26 Apr 2017 01:12:28 -0700, by Michael Pavone
-
Handle address register displacement when calculating branch targets in debuggerWed, 26 Apr 2017 01:05:40 -0700, by Michael Pavone
-
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switchingMon, 24 Apr 2017 20:49:31 -0700, by Michael Pavone
-
Add config file option to disable Open GL renderingSun, 23 Apr 2017 00:54:33 -0700, by Michael Pavone
-
Fix vgmplay target for ternary tree changesSat, 22 Apr 2017 01:22:47 -0700, by Michael Pavone
-
Fix a deficiency in the way types were handled in my ternary tree. Fixes in which some paths that were constructed from a template with variables would sometimes get an extra garbage character thrown inFri, 21 Apr 2017 23:35:32 -0700, by Michael Pavone
-
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work rightFri, 21 Apr 2017 01:22:52 -0700, by Michael Pavone
-
Minor optimization to avoid invalidating translated code when the bank has not actually changed. Makes a nasty edge case in the 68K debugger slightly less severe when dealing with code that uses bankingFri, 21 Apr 2017 01:19:40 -0700, by Michael Pavone
-
Fixed timing for RTS and RTEThu, 20 Apr 2017 22:28:58 -0700, by Michael Pavone
-
Initial stab at implementing the output disable/layer selection bits of the VDP test registerTue, 18 Apr 2017 19:27:10 -0700, by Michael Pavone
-
Fix time 68K is locked out of bus when doing a 128KB VRAM mode DMA transfer. Fixes a number of problems in Overdrive 2Mon, 17 Apr 2017 23:58:21 -0700, by Michael Pavone
-
SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2Mon, 17 Apr 2017 20:54:33 -0700, by Michael Pavone
-
Fix some edge cases with regards to 128KB VRAM mode and the SAT cacheSun, 16 Apr 2017 18:43:34 -0700, by Michael Pavone