Mercurial > repos > blastem
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Fix swapSat, 29 Dec 2012 23:40:30 -0800, by Mike Pavone
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Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixedSat, 29 Dec 2012 23:08:14 -0800, by Mike Pavone
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Fix crash when printing error message about modified return addressSat, 29 Dec 2012 23:07:23 -0800, by Mike Pavone
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Fix check in translate_m68k_src that deals with instructions for which both operands are registers that are not mapped to a native x86-64 registerSat, 29 Dec 2012 22:22:53 -0800, by Mike Pavone
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Fix encoding of movsx instruction when used with new (i.e. r9-r15) registers. This fixes the indexed addressing modes when used with a word-wide index registerSat, 29 Dec 2012 22:11:28 -0800, by Mike Pavone
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Some fixes for translating code in located in RAMSat, 29 Dec 2012 21:55:42 -0800, by Mike Pavone
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Implement the rest of the bit instructionsSat, 29 Dec 2012 21:10:07 -0800, by Mike Pavone
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Implemented ROL and RORSat, 29 Dec 2012 20:33:39 -0800, by Mike Pavone
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Fix logic for switching between USP and SSPSat, 29 Dec 2012 12:52:19 -0800, by Mike Pavone
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Fix decoding of CMPAFri, 28 Dec 2012 22:47:22 -0800, by Mike Pavone
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Fix return address pushed to stack for jsrFri, 28 Dec 2012 22:47:10 -0800, by Mike Pavone
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cycles should return dstFri, 28 Dec 2012 21:36:22 -0800, by Mike Pavone
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Fix call_r in gen_x86 so that it properly returns a pointer to the location after the generated instructionFri, 28 Dec 2012 21:25:00 -0800, by Mike Pavone
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Implement pea (untested).Fri, 28 Dec 2012 21:20:14 -0800, by Mike Pavone
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Fix Z80 busreq logicFri, 28 Dec 2012 20:46:29 -0800, by Mike Pavone
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Allow jmp/jsr to follow pc-relative addresses in disassemblerFri, 28 Dec 2012 19:21:05 -0800, by Mike Pavone
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Defer the correct address for pc relative jsr/jmpFri, 28 Dec 2012 17:59:41 -0800, by Mike Pavone
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Implement scc (untested)Fri, 28 Dec 2012 17:57:43 -0800, by Mike Pavone
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Fix decoding of SccFri, 28 Dec 2012 15:34:24 -0800, by Mike Pavone
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Implement more address modes for jsrFri, 28 Dec 2012 15:16:36 -0800, by Mike Pavone
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COmment out fifo full debug printfFri, 28 Dec 2012 15:04:22 -0800, by Mike Pavone
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Fix horizontal mask values for scroll plane map address calculationFri, 28 Dec 2012 15:03:00 -0800, by Mike Pavone
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Fix areg indexed mode for move dstFri, 28 Dec 2012 14:30:25 -0800, by Mike Pavone
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Implement ORI to CCR/SRFri, 28 Dec 2012 11:07:13 -0800, by Mike Pavone
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Implemented move from SRFri, 28 Dec 2012 10:37:09 -0800, by Mike Pavone
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Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmpThu, 27 Dec 2012 23:00:11 -0800, by Mike Pavone
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allocate a new native code chunk when we run out of spaceThu, 27 Dec 2012 22:41:28 -0800, by Mike Pavone
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Some fixes to add/addx sub/subx decodingThu, 27 Dec 2012 22:35:26 -0800, by Mike Pavone
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Implement areg indexed mode for leaThu, 27 Dec 2012 22:11:26 -0800, by Mike Pavone
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Allow use of indexed modes as move dstThu, 27 Dec 2012 22:05:22 -0800, by Mike Pavone
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Allow indexed modes to be used as a destinationThu, 27 Dec 2012 21:54:54 -0800, by Mike Pavone
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Fix address register indexed addressing (probably)Thu, 27 Dec 2012 21:32:00 -0800, by Mike Pavone
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Fix pc indexed addressing (probably) when used as a sourceThu, 27 Dec 2012 21:23:55 -0800, by Mike Pavone
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Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decodingThu, 27 Dec 2012 21:19:58 -0800, by Mike Pavone
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Fix decoding bug for addq/subqThu, 27 Dec 2012 18:47:33 -0800, by Mike Pavone
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Implement EXT, add some fixes to LINK/UNLKThu, 27 Dec 2012 18:21:10 -0800, by Mike Pavone
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Fix some bugs in emulation of CLRThu, 27 Dec 2012 10:40:03 -0800, by Mike Pavone
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Fix decoding bug in addq/subqThu, 27 Dec 2012 10:10:23 -0800, by Mike Pavone
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Fix decoding of andWed, 26 Dec 2012 22:13:31 -0800, by Mike Pavone
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Minor joypad fix and commeount out some debug printfsWed, 26 Dec 2012 22:07:44 -0800, by Mike Pavone
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Forgot to add blastem main file earlierWed, 26 Dec 2012 21:50:48 -0800, by Mike Pavone
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vertical interrupts now workWed, 26 Dec 2012 20:18:58 -0800, by Mike Pavone
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RTE doesn't crash the emulator anymoreWed, 26 Dec 2012 18:20:23 -0800, by Mike Pavone
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Fix Z80 BUSREQ/RESET implementation.Wed, 26 Dec 2012 17:50:24 -0800, by Mike Pavone
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Fix long reads from IO ports or long reads that trigger sync cycles by saving rdi. Possibly fix word wide IO reads.Wed, 26 Dec 2012 17:34:59 -0800, by Mike Pavone
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Implement Z80 reset and bus request registers.Wed, 26 Dec 2012 17:06:34 -0800, by Mike Pavone
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Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).Wed, 26 Dec 2012 11:09:04 -0800, by Mike Pavone
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Add support for indexed modes as a source, some work on jmp and jsr with areg indirect modeSat, 22 Dec 2012 21:37:25 -0800, by Mike Pavone
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Fix bug in disassembler that caused it to disassemble addresses it shouldn'tFri, 21 Dec 2012 22:33:24 -0800, by Mike Pavone
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Implement indexed with 8-bit displacement addressing modes in decoder and disassemblerFri, 21 Dec 2012 22:24:45 -0800, by Mike Pavone
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Added untested support for LINK and UNLKFri, 21 Dec 2012 21:53:05 -0800, by Mike Pavone
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Removed some old debug printfsFri, 21 Dec 2012 21:26:16 -0800, by Mike Pavone
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Implement JSR for some addressing modesFri, 21 Dec 2012 21:19:03 -0800, by Mike Pavone
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Implement DMA (untested)Fri, 21 Dec 2012 20:56:32 -0800, by Mike Pavone
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Fix some bugs in movem with a register list destinationFri, 21 Dec 2012 16:38:40 -0800, by Mike Pavone
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Implement a couple of supervisor instructionsFri, 21 Dec 2012 16:04:41 -0800, by Mike Pavone
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Implement word wide access to IO areaFri, 21 Dec 2012 16:04:30 -0800, by Mike Pavone
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Implement more instructions and address modesFri, 21 Dec 2012 01:00:52 -0800, by Mike Pavone
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Make the translator bail out if it hits an instruction I haven't implemented yetThu, 20 Dec 2012 09:17:31 -0800, by Mike Pavone
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Fix disassembly of reg list in MOVEM when the reg list is the destinationThu, 20 Dec 2012 09:12:24 -0800, by Mike Pavone
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Fix decoding and disassembly of MOVEMThu, 20 Dec 2012 09:08:13 -0800, by Mike Pavone
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Fix BTSTThu, 20 Dec 2012 00:56:33 -0800, by Mike Pavone
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Gamepad supportThu, 20 Dec 2012 00:44:59 -0800, by Mike Pavone
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Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.Wed, 19 Dec 2012 22:15:16 -0800, by Mike Pavone
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Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaultsWed, 19 Dec 2012 21:25:39 -0800, by Mike Pavone
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Add FPS counter to console outputWed, 19 Dec 2012 20:53:59 -0800, by Mike Pavone
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Print out large immediate values in hex rather than decimal formWed, 19 Dec 2012 20:53:45 -0800, by Mike Pavone
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Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.Wed, 19 Dec 2012 20:23:59 -0800, by Mike Pavone
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Fix operand order for AND instructionsTue, 18 Dec 2012 23:55:10 -0800, by Mike Pavone
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ecx was getting clobbered before the relevant temp value was used in some cases during memory readsTue, 18 Dec 2012 22:56:04 -0800, by Mike Pavone
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Properly zero-init all VDP buffers. Comment out some debug printfs.Tue, 18 Dec 2012 22:20:25 -0800, by Mike Pavone
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Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.Tue, 18 Dec 2012 22:19:52 -0800, by Mike Pavone
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Fix CRAM and possibly VSRAM writesTue, 18 Dec 2012 19:51:33 -0800, by Mike Pavone
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Add palette debug to SDL rendererTue, 18 Dec 2012 19:51:17 -0800, by Mike Pavone
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Get Flavio's color bar demo kind of sort of workingTue, 18 Dec 2012 02:16:42 -0800, by Mike Pavone
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Add preliminary support for JMPSun, 16 Dec 2012 22:25:29 -0800, by Mike Pavone
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Implement CLR, minor refactor of register offset calculation in context structSun, 16 Dec 2012 21:57:52 -0800, by Mike Pavone
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Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.Sat, 15 Dec 2012 23:01:32 -0800, by Mike Pavone
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Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructionsThu, 13 Dec 2012 09:47:40 -0800, by Mike Pavone
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Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinationsWed, 12 Dec 2012 23:21:11 -0800, by Mike Pavone
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Don't try to disassemble addresses beyond the end of the cartridgeWed, 12 Dec 2012 21:25:31 -0800, by Mike Pavone
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Fix bug in address visitation in disassemblerWed, 12 Dec 2012 20:43:42 -0800, by Mike Pavone
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Add support for dbcc instructionWed, 12 Dec 2012 20:18:06 -0800, by Mike Pavone
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Add vector table to test.s68Wed, 12 Dec 2012 20:17:59 -0800, by Mike Pavone
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Add logic for following control flow based on logic in the translatorWed, 12 Dec 2012 20:17:11 -0800, by Mike Pavone
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Add debug render mode and fix vertical flip bit for bg tilesSun, 09 Dec 2012 18:40:45 -0800, by Mike Pavone
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Fix bug in tile address masking. Remove some debug code from window plane.Sun, 09 Dec 2012 17:26:36 -0800, by Mike Pavone
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More correct window support, maybeSun, 09 Dec 2012 17:10:08 -0800, by Mike Pavone
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Broken window supportSun, 09 Dec 2012 17:05:13 -0800, by Mike Pavone
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Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it shouldSun, 09 Dec 2012 01:13:41 -0800, by Mike Pavone
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Implement sprite index >= sprite limit triggers sprite limit behaviorSun, 09 Dec 2012 00:03:15 -0800, by Mike Pavone
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Initial H32 mode supportSat, 08 Dec 2012 23:49:51 -0800, by Mike Pavone
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Pass all sprite masking testsSat, 08 Dec 2012 23:09:40 -0800, by Mike Pavone
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Small fix to overflow flagSat, 08 Dec 2012 23:06:13 -0800, by Mike Pavone
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Improve sprite masking to almost completely pass Nemesis' sprite masking testSat, 08 Dec 2012 22:50:14 -0800, by Mike Pavone
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Add support for simple resolution scalingSat, 08 Dec 2012 22:07:25 -0800, by Mike Pavone
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Fix horizontal sprite mirroringSat, 08 Dec 2012 21:39:01 -0800, by Mike Pavone
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Make horizontal scrolling closer to correct, Comix Zone looks good, Sonic 2 slightly offSat, 08 Dec 2012 20:25:56 -0800, by Mike Pavone
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Small cleanupSat, 08 Dec 2012 20:02:10 -0800, by Mike Pavone
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Fix horizontal scroll offsetSat, 08 Dec 2012 19:59:32 -0800, by Mike Pavone
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Fix BG plane B render bugSat, 08 Dec 2012 19:42:07 -0800, by Mike Pavone
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Fix sprite transparency for overlapping spritesSat, 08 Dec 2012 16:58:11 -0800, by Mike Pavone
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Fix management of context->sprite_draws so the sprite layer only draws when it shouldSat, 08 Dec 2012 16:46:47 -0800, by Mike Pavone
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Fix vertical scroll value for plane BSat, 08 Dec 2012 16:16:18 -0800, by Mike Pavone
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Partially fix BG plane BSat, 08 Dec 2012 16:09:43 -0800, by Mike Pavone
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Fix endianness of VSRAM when read from Genecyst save stateSat, 08 Dec 2012 16:02:17 -0800, by Mike Pavone
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Sprites fixed, working on bg planesSat, 08 Dec 2012 11:59:50 -0800, by Mike Pavone
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Sprites somewhat less brokenSat, 08 Dec 2012 11:12:17 -0800, by Mike Pavone
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Mostly broken VDP core and savestate viewerSat, 08 Dec 2012 02:00:54 -0800, by Mike Pavone
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Initial support for M68k reset vector, rather than starting at an arbitrary addressTue, 04 Dec 2012 19:25:54 -0800, by Mike Pavone
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M68K to x86 translation works for a limited subset of instructions and addressing modesTue, 04 Dec 2012 19:13:12 -0800, by Mike Pavone
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Add asssembly runtime code stubTue, 27 Nov 2012 22:54:38 -0800, by Mike Pavone
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Add MakefileTue, 27 Nov 2012 22:50:09 -0800, by Mike Pavone
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Make x86 generator generic with respect to operand size for immediate parameters.Tue, 27 Nov 2012 22:43:32 -0800, by Mike Pavone
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x86 code gen, initial work on translatorTue, 27 Nov 2012 09:28:13 -0800, by Mike Pavone
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Improve disassembly. FIx some decoding bugs.Thu, 15 Nov 2012 22:15:43 -0800, by Mike Pavone
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Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.Thu, 15 Nov 2012 00:52:53 -0800, by Mike Pavone
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Implement OR_DIV_SBCD group in decoderWed, 14 Nov 2012 23:04:55 -0800, by Mike Pavone
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Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special casesWed, 14 Nov 2012 09:24:40 -0800, by Mike Pavone
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Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD groupTue, 13 Nov 2012 18:26:43 -0800, by Mike Pavone
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Finish bit/movep/immediate group except for 68020 instructionsFri, 09 Nov 2012 22:01:26 -0800, by Mike Pavone
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mergeTue, 06 Nov 2012 02:07:45 -0800, by Mike Pavone
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Add some logic analyzer captures, a Python script for analyzing said captures and a higher level analysis of the outputTue, 06 Nov 2012 01:57:36 -0800, by Mike Pavone
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More bit and immediate instructionsTue, 06 Nov 2012 02:04:42 -0800, by Mike Pavone
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Add support for some bit instructions and a few others in the same "category"Sun, 04 Nov 2012 23:43:03 -0800, by Mike Pavone
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Finish mulu.w, muls.w and abcd parameter decodingSat, 03 Nov 2012 22:15:55 -0700, by Mike Pavone
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Improve 68K instruction decoding. Add simple disassembler.Sat, 03 Nov 2012 21:38:28 -0700, by Mike Pavone
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Make sure all operations are long-word length on fib example.Sat, 03 Nov 2012 21:37:38 -0700, by Mike Pavone
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Initial work on M68K instruction decodingMon, 29 Oct 2012 01:18:38 -0700, by Mike Pavone