Mercurial > repos > blastem
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Show absolute addresses for JR, JRCC and DJNZ in Z80 disassemblerThu, 09 May 2013 19:38:28 -0700, by Mike Pavone
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Fix terminal instruction detection in disassemblerThu, 09 May 2013 19:24:18 -0700, by Mike Pavone
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Properly handle instructions that use boty IYH and IYLThu, 09 May 2013 18:36:21 -0700, by Mike Pavone
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Set the N flag to the correct value for DEC instructionsThu, 09 May 2013 00:33:06 -0700, by Mike Pavone
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Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.Thu, 09 May 2013 00:30:55 -0700, by Mike Pavone
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Correctly set the N flag for SBCThu, 09 May 2013 00:17:12 -0700, by Mike Pavone
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86Thu, 09 May 2013 00:14:54 -0700, by Mike Pavone
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Complete flag behavior for Z80 BIT instructionWed, 08 May 2013 23:44:49 -0700, by Mike Pavone
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Properly handle negative displacements in Z80 coreWed, 08 May 2013 23:31:19 -0700, by Mike Pavone
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Contrary to the official documenation, OR and AND also set PV based on parity instead of overflowWed, 08 May 2013 23:29:21 -0700, by Mike Pavone
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Set PV flag based on parity, not overflow for XORWed, 08 May 2013 23:20:41 -0700, by Mike Pavone
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BIT was setting the zero flag to the opposite of what it should have. This is now fixed.Wed, 08 May 2013 23:17:54 -0700, by Mike Pavone
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More fixes for confusion between Z80_UNUSED and MODE_UNUSEDWed, 08 May 2013 23:12:08 -0700, by Mike Pavone
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Compare src_op.mode with the correct constant in shift/rotate instructionsWed, 08 May 2013 23:03:18 -0700, by Mike Pavone
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Fix IX/IY register selection when the direction bit is setWed, 08 May 2013 22:49:50 -0700, by Mike Pavone
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Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.Wed, 08 May 2013 22:46:03 -0700, by Mike Pavone
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Fix handling of instructions that combine an IX/IY displacement with another prefix in test generatorWed, 08 May 2013 22:45:29 -0700, by Mike Pavone
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Fix printing of negative displacements in Z80 disassemblerWed, 08 May 2013 22:43:31 -0700, by Mike Pavone
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Fix encoding of "extended" instructions in Z80 test generatorWed, 08 May 2013 21:02:33 -0700, by Mike Pavone
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Fix stupid copy-pasta bug in XORWed, 08 May 2013 17:39:13 -0700, by Mike Pavone
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Fix byte order of pop AFWed, 08 May 2013 17:32:28 -0700, by Mike Pavone
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Cleanup reg printing in z80 test runnerWed, 08 May 2013 17:05:12 -0700, by Mike Pavone
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Added z80 test generator and z80 test runner.Wed, 08 May 2013 14:40:48 -0700, by Mike Pavone
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Make sure all rendering operations mask CRAM with 0xEEE before using itMon, 06 May 2013 00:57:56 -0700, by Mike Pavone
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Implement writes from Z80 to YM-2612Mon, 06 May 2013 00:54:58 -0700, by Mike Pavone
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Hopefully more correct implementation of the Z80 busack statusMon, 06 May 2013 00:22:24 -0700, by Mike Pavone
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Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.Sun, 05 May 2013 22:56:42 -0700, by Mike Pavone
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Implement RRD and implement flags on RLDSun, 05 May 2013 11:17:37 -0700, by Mike Pavone
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Implemente RLDSat, 04 May 2013 18:51:53 -0700, by Mike Pavone
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Implement HALT (sort of tested)Sat, 04 May 2013 16:23:28 -0700, by Mike Pavone
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Implement IN and OUT (untested)Sat, 04 May 2013 15:58:15 -0700, by Mike Pavone
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Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.Sat, 04 May 2013 15:15:55 -0700, by Mike Pavone
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Remove deferred address entries from abandoned translations inside z80_retrans_instSat, 04 May 2013 14:36:50 -0700, by Mike Pavone
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Save context in z80_do_syncFri, 03 May 2013 21:22:36 -0700, by Mike Pavone
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Fix bank register updateFri, 03 May 2013 21:09:48 -0700, by Mike Pavone
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Fix native address lookup in bannked memory areaFri, 03 May 2013 20:18:28 -0700, by Mike Pavone
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Use hex where appropriate in disassemblerFri, 03 May 2013 20:15:23 -0700, by Mike Pavone
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Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the callerFri, 03 May 2013 19:27:32 -0700, by Mike Pavone
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Fix crash bug in Z80 interrupt supportFri, 03 May 2013 18:50:16 -0700, by Mike Pavone
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Implement shift instructions (untested)Fri, 03 May 2013 18:49:48 -0700, by Mike Pavone
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Implement CPL and NEG (untested)Thu, 02 May 2013 22:39:39 -0700, by Mike Pavone
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Implement LDD and LDDRThu, 02 May 2013 22:28:40 -0700, by Mike Pavone
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Implement LDIThu, 02 May 2013 22:26:47 -0700, by Mike Pavone
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Protect debug prints for busreq/reset regs with appropriate macrosThu, 02 May 2013 22:21:41 -0700, by Mike Pavone
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Fix decoding of CP.Thu, 02 May 2013 22:18:33 -0700, by Mike Pavone
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Fix IX/IY displace modes. Fix check for registers requiring REX.Thu, 02 May 2013 22:18:22 -0700, by Mike Pavone
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Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 resetThu, 02 May 2013 21:54:04 -0700, by Mike Pavone
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Don't mix *H regs with the REX prefixThu, 02 May 2013 00:10:24 -0700, by Mike Pavone
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Fix some more retranslation bugs in the Z80 coreWed, 01 May 2013 23:12:29 -0700, by Mike Pavone
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Add -n flag for disabling the Z80 coreWed, 01 May 2013 20:15:33 -0700, by Mike Pavone
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Fix a crash bug in instruction retranslationWed, 01 May 2013 20:09:53 -0700, by Mike Pavone
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Add a second context pointer to m68k_context so that try_fifo_write can still have easy access to the VDP. Handle writes to Z80 code addresses from the 68K.Tue, 30 Apr 2013 20:36:15 -0700, by Mike Pavone
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Implement ld to and from the I and R registersTue, 30 Apr 2013 20:33:30 -0700, by Mike Pavone
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Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_writeTue, 30 Apr 2013 01:00:10 -0700, by Mike Pavone
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Initial stab at integartiong Z80 coreTue, 30 Apr 2013 00:39:31 -0700, by Mike Pavone
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Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.Tue, 30 Apr 2013 00:39:20 -0700, by Mike Pavone
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Fix infinite loop in Z80 disassemblerTue, 30 Apr 2013 00:37:30 -0700, by Mike Pavone
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Implement CCF and SCFMon, 29 Apr 2013 23:02:39 -0700, by Mike Pavone
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Fix decoding of address in JP and JPCC instructions in the Z80 coreMon, 29 Apr 2013 22:58:45 -0700, by Mike Pavone
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Properly handle wrapping around to 0 in translate_z80_streamMon, 29 Apr 2013 22:52:05 -0700, by Mike Pavone
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Fix bug in end condition inside translate_z80_stream.Mon, 29 Apr 2013 22:37:47 -0700, by Mike Pavone
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Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.Mon, 29 Apr 2013 22:32:21 -0700, by Mike Pavone
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.Mon, 29 Apr 2013 21:46:48 -0700, by Mike Pavone
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Fix target cycle count after 68K interruptMon, 29 Apr 2013 01:14:24 -0700, by Mike Pavone
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Implemented basic interrupt support in Z80 core.Mon, 29 Apr 2013 00:59:50 -0700, by Mike Pavone
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Forgot to commit zruntime a while back, adding it now.Mon, 29 Apr 2013 00:59:32 -0700, by Mike Pavone
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Implement ADC and SBC in Z80 core (untested)Sun, 28 Apr 2013 23:25:18 -0700, by Mike Pavone
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Implement rotation and bit set/reset instructions (untested).Sun, 28 Apr 2013 22:41:30 -0700, by Mike Pavone
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Implement RETCC in Z80 core.Sun, 28 Apr 2013 21:00:27 -0700, by Mike Pavone
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Implement cartridge rom loading in transz80Sun, 28 Apr 2013 21:00:16 -0700, by Mike Pavone
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Implement cycle limit in Z80 core.Sun, 28 Apr 2013 18:53:43 -0700, by Mike Pavone
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Implement EI, DI and IM in the Z80 coreSun, 28 Apr 2013 14:32:45 -0700, by Mike Pavone
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Implemente CP (untested)Sun, 28 Apr 2013 14:05:02 -0700, by Mike Pavone
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Implement EX, EXX and RST in Z80 coreSun, 28 Apr 2013 13:45:17 -0700, by Mike Pavone
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Add header dependencies to offsetsSun, 28 Apr 2013 13:45:00 -0700, by Mike Pavone
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Implement BIT and DJNZ (tested). Fix register mapping for IYL.Fri, 26 Apr 2013 22:27:17 -0700, by Mike Pavone
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Added the rest of the conditions to JPCC, implemented CALLCC (untested)Fri, 26 Apr 2013 09:51:57 -0700, by Mike Pavone
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Added key to save Z80 RAM to a fileFri, 26 Apr 2013 09:51:13 -0700, by Mike Pavone
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Implement more Z80 instructions (untested)Thu, 25 Apr 2013 22:49:36 -0700, by Mike Pavone
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Get Z80 core working for simple programsThu, 25 Apr 2013 21:01:11 -0700, by Mike Pavone
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Add shadow/higlight info to debug rendererMon, 22 Apr 2013 23:56:13 -0700, by Mike Pavone
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Less broken implementation of shadow/highlightMon, 22 Apr 2013 23:34:39 -0700, by Mike Pavone
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Shadow and higlight operators were switchedMon, 22 Apr 2013 21:24:50 -0700, by Mike Pavone
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Added todo listMon, 22 Apr 2013 20:13:07 -0700, by Mike Pavone
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Implemented shadow hilight mode.Mon, 22 Apr 2013 19:39:38 -0700, by Mike Pavone
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Improve color rendering accuracy and optimize SDL renderer a bitSun, 21 Apr 2013 19:12:48 -0700, by Mike Pavone
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Fix overflow detection in divs. Fix negative immediate source for divsSun, 21 Apr 2013 16:44:46 -0700, by Mike Pavone
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Added test cases for divs/divu and added divide by zero handler to test generatorSun, 21 Apr 2013 16:44:10 -0700, by Mike Pavone
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Implement CHK instruction (not fully tested).Sun, 21 Apr 2013 13:00:34 -0700, by Mike Pavone
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Added testcases for move and roxl/roxr. Made some small improvements to test tools.Sun, 21 Apr 2013 11:40:18 -0700, by Mike Pavone
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Fix muls with a negative immediate source.Sat, 20 Apr 2013 17:41:07 -0700, by Mike Pavone
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Added testcases for muls, mulu, abcd and sbcdSat, 20 Apr 2013 17:32:34 -0700, by Mike Pavone
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Fix modulo on bit operations with a memory destinationSat, 20 Apr 2013 16:53:01 -0700, by Mike Pavone
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Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions.Sat, 20 Apr 2013 15:14:47 -0700, by Mike Pavone
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Fix overflow flag behavior for lsl/lsr/asrSat, 20 Apr 2013 14:36:41 -0700, by Mike Pavone
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Fix autoincrement on a7 when used as a destination in a byte sized instructionSat, 20 Apr 2013 00:36:50 -0700, by Mike Pavone
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Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.Sat, 20 Apr 2013 00:29:14 -0700, by Mike Pavone
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Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.Fri, 19 Apr 2013 21:36:54 -0700, by Mike Pavone
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Added headless flag to avoid initializing SDL and opening a window when running tests.Fri, 19 Apr 2013 21:36:00 -0700, by Mike Pavone
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Add test generator, builder and runnerFri, 19 Apr 2013 09:29:37 -0700, by Mike Pavone
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Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.Tue, 16 Apr 2013 22:29:00 -0700, by Mike Pavone
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Fixed up trans for changes to translate_m68k_stream, but still need to deal with missing callbacks.Tue, 16 Apr 2013 09:38:30 -0700, by Mike Pavone
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Small bit of cleanupTue, 16 Apr 2013 09:31:21 -0700, by Mike Pavone
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Fix movem reg to mem for certain addressing modesSun, 27 Jan 2013 13:07:26 -0800, by Mike Pavone
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Flag fixes for div, negx and notSat, 26 Jan 2013 02:47:26 -0800, by Mike Pavone
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Tweaks to make blastem compatible with m68k-testerSat, 26 Jan 2013 01:33:32 -0800, by Mike Pavone
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Fix overflow flag on ASLFri, 25 Jan 2013 18:39:22 -0800, by Mike Pavone
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Add support for IY bit instructions to decoderWed, 23 Jan 2013 21:54:58 -0800, by Mike Pavone
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Add support for IX bit instructions to decoderWed, 23 Jan 2013 21:50:54 -0800, by Mike Pavone
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Add support for 2-byte IY instructions to decoderTue, 22 Jan 2013 20:24:14 -0800, by Mike Pavone
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Add support for 2-byte IX instructions to decoderTue, 22 Jan 2013 20:21:05 -0800, by Mike Pavone
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Distinguish between 1-byte and 2-byte NOPsMon, 21 Jan 2013 21:59:09 -0800, by Mike Pavone
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Add support for bit instructions to decoderMon, 21 Jan 2013 21:17:52 -0800, by Mike Pavone
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Add support for EXTD group 2-byte Z80 instructions in decoderSun, 20 Jan 2013 21:32:13 -0800, by Mike Pavone
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Add initial stab at Z80 decoder and disassemblerSun, 20 Jan 2013 19:11:24 -0800, by Mike Pavone
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Add support for breaking into the debugger while game is runningSun, 20 Jan 2013 19:10:29 -0800, by Mike Pavone
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Add instruction address logging to translator and support for reading an address log to the disassemblerThu, 17 Jan 2013 20:00:07 -0800, by Mike Pavone
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Implement pc indexed mode as move dstThu, 17 Jan 2013 08:19:29 -0800, by Mike Pavone
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Fix 6-button controller emulationWed, 16 Jan 2013 22:50:02 -0800, by Mike Pavone
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Implement ABCD an SBCD. Fix BTEST with register source.Wed, 16 Jan 2013 22:40:56 -0800, by Mike Pavone
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Implement support for self-modifying codeTue, 15 Jan 2013 00:14:36 -0800, by Mike Pavone
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Prep work for handling games that modify code in RAMMon, 14 Jan 2013 21:56:54 -0800, by Mike Pavone
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Fixes for direct color dma stuffMon, 14 Jan 2013 20:23:17 -0800, by Mike Pavone
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Small fix to bg drawing that yields the proper res for direct color DMAMon, 14 Jan 2013 02:13:14 -0800, by Mike Pavone
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Fix background rendering when display is off and improve refresh cycle emulation so that direct color DMA demos workMon, 14 Jan 2013 02:03:35 -0800, by Mike Pavone
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Fix movem.w when dest is register listSun, 13 Jan 2013 23:48:04 -0800, by Mike Pavone
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Fix return address for areg displacement mode JSRSun, 13 Jan 2013 23:06:26 -0800, by Mike Pavone
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Cleanup VINT code and fix bug in which VINT cycle would be set incorrectly after a VDP control port writeSun, 13 Jan 2013 16:11:28 -0800, by Mike Pavone
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Add ability to print out current 68K cycle in debuggerSun, 13 Jan 2013 15:55:43 -0800, by Mike Pavone
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Fix a bunch of bugs in the CPU core, add a 68K debuggerSun, 13 Jan 2013 13:01:13 -0800, by Mike Pavone
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Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalidWed, 09 Jan 2013 22:31:07 -0800, by Mike Pavone
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Fix -(a7) dest when size is byteWed, 09 Jan 2013 21:41:55 -0800, by Mike Pavone
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Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructionsWed, 09 Jan 2013 21:08:37 -0800, by Mike Pavone
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Fix rendering of sprites at the top edge of screenTue, 08 Jan 2013 09:34:46 -0800, by Mike Pavone
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Fix scc to set reg to 0xFF rather than 1 when the condition is trueTue, 08 Jan 2013 09:34:24 -0800, by Mike Pavone
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Fix order of reading saved pc and swapping user and system stack pointersSun, 06 Jan 2013 22:45:45 -0800, by Mike Pavone
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Make sure we bail out of translation after translating an invalid instructionSun, 06 Jan 2013 21:44:54 -0800, by Mike Pavone
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Print a message when we try to run an invalid instruction, not when we try to translate itSun, 06 Jan 2013 21:42:57 -0800, by Mike Pavone
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Fix order of SR and PC saved in an exception stack frameSun, 06 Jan 2013 20:49:42 -0800, by Mike Pavone
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Implement areg displacement mode for jsrSun, 06 Jan 2013 18:31:17 -0800, by Mike Pavone
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Implement negxSun, 06 Jan 2013 15:20:23 -0800, by Mike Pavone
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Implement movepSun, 06 Jan 2013 14:41:26 -0800, by Mike Pavone
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Implement EORI CCR/SRSun, 06 Jan 2013 14:00:45 -0800, by Mike Pavone
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Implement RTRSun, 06 Jan 2013 13:58:33 -0800, by Mike Pavone
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Fix a bunch of addressing modes in movem when a register list is the destinationSun, 06 Jan 2013 13:42:13 -0800, by Mike Pavone
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Minor optimization and a cycle count fix to leaSun, 06 Jan 2013 12:17:10 -0800, by Mike Pavone
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Initialize status register to proper value on startupSun, 06 Jan 2013 10:54:45 -0800, by Mike Pavone
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Added SMD ROM supportSun, 06 Jan 2013 09:51:15 -0800, by Mike Pavone
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Fix certain address modes with lea when the destination is not a native registerSat, 05 Jan 2013 22:59:51 -0800, by Mike Pavone
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Small fix to disassemblerSat, 05 Jan 2013 22:59:06 -0800, by Mike Pavone
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Fix decoding of movepSat, 05 Jan 2013 02:46:55 -0800, by Mike Pavone
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Implement more movem modes srcSat, 05 Jan 2013 02:18:31 -0800, by Mike Pavone
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Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dstSat, 05 Jan 2013 01:55:11 -0800, by Mike Pavone
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Fix crash in printf from "crash" function due to lack of clearing raxSat, 05 Jan 2013 01:32:40 -0800, by Mike Pavone
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FIx movem when src is reg list and dst is not a areg predec modeSat, 05 Jan 2013 01:31:28 -0800, by Mike Pavone
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Fix predec address mode when used as sourceSat, 05 Jan 2013 00:53:50 -0800, by Mike Pavone
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Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.Fri, 04 Jan 2013 23:52:20 -0800, by Mike Pavone
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Add cycles for Bcc (needs work, but this changes keeps some ROMs from making the emulator unresponsive)Fri, 04 Jan 2013 23:25:23 -0800, by Mike Pavone
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Don't use the native call stack for M68K calls by defaultFri, 04 Jan 2013 23:21:07 -0800, by Mike Pavone
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Small fix for bit instructionsFri, 04 Jan 2013 22:51:01 -0800, by Mike Pavone
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Implement access to Z80 RAMFri, 04 Jan 2013 21:47:09 -0800, by Mike Pavone
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Implement TRAP (untested)Thu, 03 Jan 2013 22:49:21 -0800, by Mike Pavone
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Implement MULU/MULS and DIVU/DIVSThu, 03 Jan 2013 22:07:40 -0800, by Mike Pavone
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Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.Tue, 01 Jan 2013 09:40:17 -0800, by Mike Pavone
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Make writes to control and data port block when DMA is in progressTue, 01 Jan 2013 07:06:57 -0800, by Mike Pavone
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Bail out of disassembly of a particular stream when we hit an invalid instructionTue, 01 Jan 2013 07:04:48 -0800, by Mike Pavone
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Add hgignore fileTue, 01 Jan 2013 07:03:52 -0800, by Mike Pavone
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Implement most of the "X" instructionsMon, 31 Dec 2012 20:09:09 -0800, by Mike Pavone
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Implement m68k_modified_ret_addrMon, 31 Dec 2012 19:17:01 -0800, by Mike Pavone
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Comment out some debug printfsMon, 31 Dec 2012 18:53:52 -0800, by Mike Pavone
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Fix infinite loop bug in sprite renderingMon, 31 Dec 2012 18:36:16 -0800, by Mike Pavone
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Fix DMA fills to VRAMMon, 31 Dec 2012 18:22:25 -0800, by Mike Pavone
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Fix DMA in progress flag in VDP status registerMon, 31 Dec 2012 18:12:08 -0800, by Mike Pavone
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Fix label names in disassemblerMon, 31 Dec 2012 11:56:01 -0800, by Mike Pavone
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Properly support references to odd addresses in label generation in disassembler. Add labels for start and interrupts.Mon, 31 Dec 2012 11:54:27 -0800, by Mike Pavone
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Fix VDP readsMon, 31 Dec 2012 11:26:57 -0800, by Mike Pavone
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Implemented HV counterSun, 30 Dec 2012 22:39:41 -0800, by Mike Pavone
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Fix some bugs in decoding cmpSun, 30 Dec 2012 18:40:33 -0800, by Mike Pavone
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Fix 68K->VDP DMASun, 30 Dec 2012 11:54:25 -0800, by Mike Pavone
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Improve disassemblerSun, 30 Dec 2012 09:55:18 -0800, by Mike Pavone
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Add support for pc indexed addressing mode to leaSun, 30 Dec 2012 09:55:07 -0800, by Mike Pavone
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Support more address modes for jmpSun, 30 Dec 2012 07:52:44 -0800, by Mike Pavone
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Fix bug that was causing DMA fills to lock up under certain circumstancesSun, 30 Dec 2012 01:15:16 -0800, by Mike Pavone
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Make version register return correct value for USASun, 30 Dec 2012 00:11:03 -0800, by Mike Pavone
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Fix swapSat, 29 Dec 2012 23:40:30 -0800, by Mike Pavone
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Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixedSat, 29 Dec 2012 23:08:14 -0800, by Mike Pavone
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Fix crash when printing error message about modified return addressSat, 29 Dec 2012 23:07:23 -0800, by Mike Pavone
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Fix check in translate_m68k_src that deals with instructions for which both operands are registers that are not mapped to a native x86-64 registerSat, 29 Dec 2012 22:22:53 -0800, by Mike Pavone
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Fix encoding of movsx instruction when used with new (i.e. r9-r15) registers. This fixes the indexed addressing modes when used with a word-wide index registerSat, 29 Dec 2012 22:11:28 -0800, by Mike Pavone
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Some fixes for translating code in located in RAMSat, 29 Dec 2012 21:55:42 -0800, by Mike Pavone
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Implement the rest of the bit instructionsSat, 29 Dec 2012 21:10:07 -0800, by Mike Pavone
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Implemented ROL and RORSat, 29 Dec 2012 20:33:39 -0800, by Mike Pavone
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Fix logic for switching between USP and SSPSat, 29 Dec 2012 12:52:19 -0800, by Mike Pavone
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Fix decoding of CMPAFri, 28 Dec 2012 22:47:22 -0800, by Mike Pavone
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Fix return address pushed to stack for jsrFri, 28 Dec 2012 22:47:10 -0800, by Mike Pavone
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cycles should return dstFri, 28 Dec 2012 21:36:22 -0800, by Mike Pavone
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Fix call_r in gen_x86 so that it properly returns a pointer to the location after the generated instructionFri, 28 Dec 2012 21:25:00 -0800, by Mike Pavone
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Implement pea (untested).Fri, 28 Dec 2012 21:20:14 -0800, by Mike Pavone
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Fix Z80 busreq logicFri, 28 Dec 2012 20:46:29 -0800, by Mike Pavone
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Allow jmp/jsr to follow pc-relative addresses in disassemblerFri, 28 Dec 2012 19:21:05 -0800, by Mike Pavone
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Defer the correct address for pc relative jsr/jmpFri, 28 Dec 2012 17:59:41 -0800, by Mike Pavone
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Implement scc (untested)Fri, 28 Dec 2012 17:57:43 -0800, by Mike Pavone
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Fix decoding of SccFri, 28 Dec 2012 15:34:24 -0800, by Mike Pavone
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Implement more address modes for jsrFri, 28 Dec 2012 15:16:36 -0800, by Mike Pavone
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COmment out fifo full debug printfFri, 28 Dec 2012 15:04:22 -0800, by Mike Pavone
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Fix horizontal mask values for scroll plane map address calculationFri, 28 Dec 2012 15:03:00 -0800, by Mike Pavone
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Fix areg indexed mode for move dstFri, 28 Dec 2012 14:30:25 -0800, by Mike Pavone
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Implement ORI to CCR/SRFri, 28 Dec 2012 11:07:13 -0800, by Mike Pavone
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Implemented move from SRFri, 28 Dec 2012 10:37:09 -0800, by Mike Pavone
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Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmpThu, 27 Dec 2012 23:00:11 -0800, by Mike Pavone
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allocate a new native code chunk when we run out of spaceThu, 27 Dec 2012 22:41:28 -0800, by Mike Pavone
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Some fixes to add/addx sub/subx decodingThu, 27 Dec 2012 22:35:26 -0800, by Mike Pavone
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Implement areg indexed mode for leaThu, 27 Dec 2012 22:11:26 -0800, by Mike Pavone
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Allow use of indexed modes as move dstThu, 27 Dec 2012 22:05:22 -0800, by Mike Pavone
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Allow indexed modes to be used as a destinationThu, 27 Dec 2012 21:54:54 -0800, by Mike Pavone
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Fix address register indexed addressing (probably)Thu, 27 Dec 2012 21:32:00 -0800, by Mike Pavone
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Fix pc indexed addressing (probably) when used as a sourceThu, 27 Dec 2012 21:23:55 -0800, by Mike Pavone
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Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decodingThu, 27 Dec 2012 21:19:58 -0800, by Mike Pavone
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Fix decoding bug for addq/subqThu, 27 Dec 2012 18:47:33 -0800, by Mike Pavone
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Implement EXT, add some fixes to LINK/UNLKThu, 27 Dec 2012 18:21:10 -0800, by Mike Pavone
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Fix some bugs in emulation of CLRThu, 27 Dec 2012 10:40:03 -0800, by Mike Pavone
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Fix decoding bug in addq/subqThu, 27 Dec 2012 10:10:23 -0800, by Mike Pavone
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Fix decoding of andWed, 26 Dec 2012 22:13:31 -0800, by Mike Pavone
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Minor joypad fix and commeount out some debug printfsWed, 26 Dec 2012 22:07:44 -0800, by Mike Pavone
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Forgot to add blastem main file earlierWed, 26 Dec 2012 21:50:48 -0800, by Mike Pavone
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vertical interrupts now workWed, 26 Dec 2012 20:18:58 -0800, by Mike Pavone
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RTE doesn't crash the emulator anymoreWed, 26 Dec 2012 18:20:23 -0800, by Mike Pavone
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Fix Z80 BUSREQ/RESET implementation.Wed, 26 Dec 2012 17:50:24 -0800, by Mike Pavone
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Fix long reads from IO ports or long reads that trigger sync cycles by saving rdi. Possibly fix word wide IO reads.Wed, 26 Dec 2012 17:34:59 -0800, by Mike Pavone
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Implement Z80 reset and bus request registers.Wed, 26 Dec 2012 17:06:34 -0800, by Mike Pavone
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Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).Wed, 26 Dec 2012 11:09:04 -0800, by Mike Pavone
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Add support for indexed modes as a source, some work on jmp and jsr with areg indirect modeSat, 22 Dec 2012 21:37:25 -0800, by Mike Pavone
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Fix bug in disassembler that caused it to disassemble addresses it shouldn'tFri, 21 Dec 2012 22:33:24 -0800, by Mike Pavone
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Implement indexed with 8-bit displacement addressing modes in decoder and disassemblerFri, 21 Dec 2012 22:24:45 -0800, by Mike Pavone
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Added untested support for LINK and UNLKFri, 21 Dec 2012 21:53:05 -0800, by Mike Pavone
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Removed some old debug printfsFri, 21 Dec 2012 21:26:16 -0800, by Mike Pavone
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Implement JSR for some addressing modesFri, 21 Dec 2012 21:19:03 -0800, by Mike Pavone
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Implement DMA (untested)Fri, 21 Dec 2012 20:56:32 -0800, by Mike Pavone
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Fix some bugs in movem with a register list destinationFri, 21 Dec 2012 16:38:40 -0800, by Mike Pavone
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Implement a couple of supervisor instructionsFri, 21 Dec 2012 16:04:41 -0800, by Mike Pavone
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Implement word wide access to IO areaFri, 21 Dec 2012 16:04:30 -0800, by Mike Pavone
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Implement more instructions and address modesFri, 21 Dec 2012 01:00:52 -0800, by Mike Pavone
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Make the translator bail out if it hits an instruction I haven't implemented yetThu, 20 Dec 2012 09:17:31 -0800, by Mike Pavone
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Fix disassembly of reg list in MOVEM when the reg list is the destinationThu, 20 Dec 2012 09:12:24 -0800, by Mike Pavone
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Fix decoding and disassembly of MOVEMThu, 20 Dec 2012 09:08:13 -0800, by Mike Pavone
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Fix BTSTThu, 20 Dec 2012 00:56:33 -0800, by Mike Pavone
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Gamepad supportThu, 20 Dec 2012 00:44:59 -0800, by Mike Pavone
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Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.Wed, 19 Dec 2012 22:15:16 -0800, by Mike Pavone
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Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaultsWed, 19 Dec 2012 21:25:39 -0800, by Mike Pavone
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Add FPS counter to console outputWed, 19 Dec 2012 20:53:59 -0800, by Mike Pavone
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Print out large immediate values in hex rather than decimal formWed, 19 Dec 2012 20:53:45 -0800, by Mike Pavone
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Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.Wed, 19 Dec 2012 20:23:59 -0800, by Mike Pavone
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Fix operand order for AND instructionsTue, 18 Dec 2012 23:55:10 -0800, by Mike Pavone
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ecx was getting clobbered before the relevant temp value was used in some cases during memory readsTue, 18 Dec 2012 22:56:04 -0800, by Mike Pavone
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Properly zero-init all VDP buffers. Comment out some debug printfs.Tue, 18 Dec 2012 22:20:25 -0800, by Mike Pavone
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Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.Tue, 18 Dec 2012 22:19:52 -0800, by Mike Pavone
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Fix CRAM and possibly VSRAM writesTue, 18 Dec 2012 19:51:33 -0800, by Mike Pavone
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Add palette debug to SDL rendererTue, 18 Dec 2012 19:51:17 -0800, by Mike Pavone
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Get Flavio's color bar demo kind of sort of workingTue, 18 Dec 2012 02:16:42 -0800, by Mike Pavone
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Add preliminary support for JMPSun, 16 Dec 2012 22:25:29 -0800, by Mike Pavone
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Implement CLR, minor refactor of register offset calculation in context structSun, 16 Dec 2012 21:57:52 -0800, by Mike Pavone
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Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.Sat, 15 Dec 2012 23:01:32 -0800, by Mike Pavone
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Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructionsThu, 13 Dec 2012 09:47:40 -0800, by Mike Pavone
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Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinationsWed, 12 Dec 2012 23:21:11 -0800, by Mike Pavone
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Don't try to disassemble addresses beyond the end of the cartridgeWed, 12 Dec 2012 21:25:31 -0800, by Mike Pavone
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Fix bug in address visitation in disassemblerWed, 12 Dec 2012 20:43:42 -0800, by Mike Pavone
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Add support for dbcc instructionWed, 12 Dec 2012 20:18:06 -0800, by Mike Pavone
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Add vector table to test.s68Wed, 12 Dec 2012 20:17:59 -0800, by Mike Pavone
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Add logic for following control flow based on logic in the translatorWed, 12 Dec 2012 20:17:11 -0800, by Mike Pavone
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Add debug render mode and fix vertical flip bit for bg tilesSun, 09 Dec 2012 18:40:45 -0800, by Mike Pavone
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Fix bug in tile address masking. Remove some debug code from window plane.Sun, 09 Dec 2012 17:26:36 -0800, by Mike Pavone
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More correct window support, maybeSun, 09 Dec 2012 17:10:08 -0800, by Mike Pavone
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Broken window supportSun, 09 Dec 2012 17:05:13 -0800, by Mike Pavone
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Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it shouldSun, 09 Dec 2012 01:13:41 -0800, by Mike Pavone
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Implement sprite index >= sprite limit triggers sprite limit behaviorSun, 09 Dec 2012 00:03:15 -0800, by Mike Pavone
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Initial H32 mode supportSat, 08 Dec 2012 23:49:51 -0800, by Mike Pavone
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Pass all sprite masking testsSat, 08 Dec 2012 23:09:40 -0800, by Mike Pavone
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Small fix to overflow flagSat, 08 Dec 2012 23:06:13 -0800, by Mike Pavone
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Improve sprite masking to almost completely pass Nemesis' sprite masking testSat, 08 Dec 2012 22:50:14 -0800, by Mike Pavone
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Add support for simple resolution scalingSat, 08 Dec 2012 22:07:25 -0800, by Mike Pavone
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Fix horizontal sprite mirroringSat, 08 Dec 2012 21:39:01 -0800, by Mike Pavone
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Make horizontal scrolling closer to correct, Comix Zone looks good, Sonic 2 slightly offSat, 08 Dec 2012 20:25:56 -0800, by Mike Pavone
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Small cleanupSat, 08 Dec 2012 20:02:10 -0800, by Mike Pavone
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Fix horizontal scroll offsetSat, 08 Dec 2012 19:59:32 -0800, by Mike Pavone
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Fix BG plane B render bugSat, 08 Dec 2012 19:42:07 -0800, by Mike Pavone
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Fix sprite transparency for overlapping spritesSat, 08 Dec 2012 16:58:11 -0800, by Mike Pavone
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Fix management of context->sprite_draws so the sprite layer only draws when it shouldSat, 08 Dec 2012 16:46:47 -0800, by Mike Pavone
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Fix vertical scroll value for plane BSat, 08 Dec 2012 16:16:18 -0800, by Mike Pavone
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Partially fix BG plane BSat, 08 Dec 2012 16:09:43 -0800, by Mike Pavone
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Fix endianness of VSRAM when read from Genecyst save stateSat, 08 Dec 2012 16:02:17 -0800, by Mike Pavone
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Sprites fixed, working on bg planesSat, 08 Dec 2012 11:59:50 -0800, by Mike Pavone
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Sprites somewhat less brokenSat, 08 Dec 2012 11:12:17 -0800, by Mike Pavone
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Mostly broken VDP core and savestate viewerSat, 08 Dec 2012 02:00:54 -0800, by Mike Pavone
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Initial support for M68k reset vector, rather than starting at an arbitrary addressTue, 04 Dec 2012 19:25:54 -0800, by Mike Pavone
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M68K to x86 translation works for a limited subset of instructions and addressing modesTue, 04 Dec 2012 19:13:12 -0800, by Mike Pavone
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Add asssembly runtime code stubTue, 27 Nov 2012 22:54:38 -0800, by Mike Pavone
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Add MakefileTue, 27 Nov 2012 22:50:09 -0800, by Mike Pavone
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Make x86 generator generic with respect to operand size for immediate parameters.Tue, 27 Nov 2012 22:43:32 -0800, by Mike Pavone
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x86 code gen, initial work on translatorTue, 27 Nov 2012 09:28:13 -0800, by Mike Pavone
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Improve disassembly. FIx some decoding bugs.Thu, 15 Nov 2012 22:15:43 -0800, by Mike Pavone
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Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.Thu, 15 Nov 2012 00:52:53 -0800, by Mike Pavone
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Implement OR_DIV_SBCD group in decoderWed, 14 Nov 2012 23:04:55 -0800, by Mike Pavone
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Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special casesWed, 14 Nov 2012 09:24:40 -0800, by Mike Pavone
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Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD groupTue, 13 Nov 2012 18:26:43 -0800, by Mike Pavone
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Finish bit/movep/immediate group except for 68020 instructionsFri, 09 Nov 2012 22:01:26 -0800, by Mike Pavone
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mergeTue, 06 Nov 2012 02:07:45 -0800, by Mike Pavone
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Add some logic analyzer captures, a Python script for analyzing said captures and a higher level analysis of the outputTue, 06 Nov 2012 01:57:36 -0800, by Mike Pavone
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More bit and immediate instructionsTue, 06 Nov 2012 02:04:42 -0800, by Mike Pavone
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Add support for some bit instructions and a few others in the same "category"Sun, 04 Nov 2012 23:43:03 -0800, by Mike Pavone
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Finish mulu.w, muls.w and abcd parameter decodingSat, 03 Nov 2012 22:15:55 -0700, by Mike Pavone
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Improve 68K instruction decoding. Add simple disassembler.Sat, 03 Nov 2012 21:38:28 -0700, by Mike Pavone
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Make sure all operations are long-word length on fib example.Sat, 03 Nov 2012 21:37:38 -0700, by Mike Pavone
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Initial work on M68K instruction decodingMon, 29 Oct 2012 01:18:38 -0700, by Mike Pavone