Mercurial > repos > blastem
graph
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Theoretically more correct timing of Z80 bus requestWed, 18 Sep 2013 19:10:54 -0700, by Mike Pavone
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Set VBLANK flag in status register when display is disabledTue, 17 Sep 2013 19:10:00 -0700, by Mike Pavone
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Implement HV counter latchTue, 17 Sep 2013 09:45:14 -0700, by Mike Pavone
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Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40Tue, 17 Sep 2013 00:42:49 -0700, by Mike Pavone
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Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.Tue, 17 Sep 2013 00:11:45 -0700, by Mike Pavone
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Partial fix for DMA copyMon, 16 Sep 2013 09:44:22 -0700, by Mike Pavone