Mercurial > repos > blastem
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Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.Tue, 17 Sep 2013 00:11:45 -0700, by Mike Pavone
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Partial fix for DMA copyMon, 16 Sep 2013 09:44:22 -0700, by Mike Pavone
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Clear the low 2 bits of CD when a register is written toSun, 15 Sep 2013 23:49:09 -0700, by Mike Pavone
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Don't allow register writes to regs above when in Mode 4Sun, 15 Sep 2013 23:40:18 -0700, by Mike Pavone
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Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11Sun, 15 Sep 2013 23:33:24 -0700, by Mike Pavone
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Implement undocumented 8-bit VRAM readSun, 15 Sep 2013 23:00:17 -0700, by Mike Pavone
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Fix VSRAM readsSun, 15 Sep 2013 22:43:01 -0700, by Mike Pavone
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Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properlySun, 15 Sep 2013 22:20:43 -0700, by Mike Pavone
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Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.Fri, 13 Sep 2013 19:22:46 -0700, by Mike Pavone
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Fix argument handling so that the rom filename does not need to be specified firstWed, 11 Sep 2013 19:26:35 -0700, by Mike Pavone
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Added copyright notice to source files and added GPL license text in COPYINGTue, 10 Sep 2013 23:31:08 -0700, by Mike Pavone
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Fix vgmplayTue, 10 Sep 2013 21:20:54 -0700, by Mike Pavone
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Fix stateview. Update "all" target in Makefile.Tue, 10 Sep 2013 21:07:13 -0700, by Mike Pavone
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Added version flagTue, 10 Sep 2013 20:36:05 -0700, by Mike Pavone
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Added -h help text optionTue, 10 Sep 2013 20:32:59 -0700, by Mike Pavone
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Fix timing of backdrop rendering when the display is turned offTue, 10 Sep 2013 09:55:12 -0700, by Mike Pavone
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MergeTue, 10 Sep 2013 00:30:39 -0700, by Mike Pavone
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Implement FIFO latency and improve DMA accuracyTue, 10 Sep 2013 00:29:46 -0700, by Mike Pavone
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Revert change to VBLANK flag timing based on new direct color DMA testSun, 08 Sep 2013 20:48:33 -0700, by Mike Pavone
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Remove extra 68K/VDP cycle syncSun, 08 Sep 2013 20:47:01 -0700, by Mike Pavone
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Fix bit instruction timingSun, 08 Sep 2013 20:46:25 -0700, by Mike Pavone
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Initial work on GDB remote debugging supportWed, 04 Sep 2013 19:34:19 -0700, by Mike Pavone
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Added analysis script used for investigating direct color DMA timingMon, 02 Sep 2013 01:03:08 -0700, by Mike Pavone
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Fix per-column scrolling bugMon, 02 Sep 2013 01:02:18 -0700, by Mike Pavone
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Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.Mon, 02 Sep 2013 00:20:56 -0700, by Mike Pavone
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MergeSun, 01 Sep 2013 14:27:17 -0700, by Mike Pavone
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Added support for saving savestates. Added gst savestate format test harnessFri, 26 Jul 2013 19:55:04 -0700, by Mike Pavone
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Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not emptySun, 01 Sep 2013 12:11:28 -0700, by Mike Pavone
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Fix handling of key on in YM2612 coreSat, 20 Jul 2013 23:49:31 -0700, by Mike Pavone
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Fix performance regression from stop instruction workSat, 20 Jul 2013 23:40:28 -0700, by Mike Pavone