Mercurial > repos > blastem
diff backend_x86.c @ 2134:9caebcfeac72
Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
author | Michael Pavone <pavone@retrodev.com> |
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date | Fri, 18 Mar 2022 20:49:07 -0700 |
parents | 8554751f17b5 |
children | b6338e18787e |
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--- a/backend_x86.c Thu Mar 17 22:41:42 2022 -0700 +++ b/backend_x86.c Fri Mar 18 20:49:07 2022 -0700 @@ -165,6 +165,29 @@ if (memmap[chunk].mask != opts->address_mask) { and_ir(code, memmap[chunk].mask, adr_reg, opts->address_size); } + code_ptr after_normal = NULL; + if (size == SZ_B && memmap[chunk].shift != 0) { + btr_ir(code, 0, adr_reg, opts->address_size); + code_ptr normal = code->cur+1; + jcc(code, CC_NC, normal); + if (memmap[chunk].shift > 0) { + shl_ir(code, memmap[chunk].shift, adr_reg, opts->address_size); + } else { + shr_ir(code, -memmap[chunk].shift, adr_reg, opts->address_size); + } + or_ir(code, 1, adr_reg, opts->address_size); + after_normal = code->cur + 1; + jmp(code, after_normal); + *normal = code->cur - (normal + 1); + } + if (memmap[chunk].shift > 0) { + shl_ir(code, memmap[chunk].shift, adr_reg, opts->address_size); + } else if (memmap[chunk].shift < 0) { + shr_ir(code, -memmap[chunk].shift, adr_reg, opts->address_size); + } + if (after_normal) { + *after_normal = code->cur - (after_normal + 1); + } void * cfun; switch (fun_type) {