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Clear EDT on DTTRG. Fixes Cliffhanger and OrionNavattan's Mode 1 demo
author Michael Pavone <pavone@retrodev.com>
date Thu, 05 Sep 2024 23:44:01 -0700
parents d44fe974fb85
children
comparison
equal deleted inserted replaced
2514:50cff4c9286e 2515:0775f5e0c468
854 case GA_CDC_CTRL: { 854 case GA_CDC_CTRL: {
855 cdd_run(cd, m68k->cycles); 855 cdd_run(cd, m68k->cycles);
856 lc8951_ar_write(&cd->cdc, value); 856 lc8951_ar_write(&cd->cdc, value);
857 //cd->gate_array[reg] &= 0xC000; 857 //cd->gate_array[reg] &= 0xC000;
858 uint16_t old_dest = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7; 858 uint16_t old_dest = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
859 //apparently this clears EDT, should it also clear DSR? 859 //clears both EDT and DSR
860 cd->gate_array[reg] = value & 0x0700; 860 cd->gate_array[reg] = value & 0x0700;
861 uint16_t dest = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7; 861 uint16_t dest = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
862 if (dest != old_dest) { 862 if (dest != old_dest) {
863 if (dest == DST_PCM_RAM) { 863 if (dest == DST_PCM_RAM) {
864 lc8951_set_dma_multiple(&cd->cdc, 21); 864 lc8951_set_dma_multiple(&cd->cdc, 21);
876 } 876 }
877 case GA_CDC_REG_DATA: 877 case GA_CDC_REG_DATA:
878 cdd_run(cd, m68k->cycles); 878 cdd_run(cd, m68k->cycles);
879 printf("CDC write %X: %X @ %u\n", cd->cdc.ar, value, m68k->cycles); 879 printf("CDC write %X: %X @ %u\n", cd->cdc.ar, value, m68k->cycles);
880 if (cd->cdc.ar == 6) { 880 if (cd->cdc.ar == 6) {
881 //this next bit needs hardware confirmation
881 cd->cdc_dst_low = 0; 882 cd->cdc_dst_low = 0;
882 //TODO: Confirm if DSR is cleared here on hardware 883 }
884 lc8951_reg_write(&cd->cdc, value);
885 if (!lc8951_dtbsy_state(&cd->cdc)) {
886 //new transfer has started, this clears EDT
887 cd->gate_array[GA_CDC_CTRL] &= ~BIT_EDT;
888 //DSR does not seem to be cleared on hardware
889 //but doing this seems to fix Penn & Teller's Smoke and Mirrors
890 //needs more research
883 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR; 891 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR;
884 } 892 }
885 lc8951_reg_write(&cd->cdc, value);
886 calculate_target_cycle(m68k); 893 calculate_target_cycle(m68k);
887 break; 894 break;
888 case GA_CDC_HOST_DATA: 895 case GA_CDC_HOST_DATA:
889 //writes to this register have the same side effects as reads 896 //writes to this register have the same side effects as reads
890 sub_gate_read16(address, vcontext); 897 sub_gate_read16(address, vcontext);
891 break; 898 break;
892 case GA_CDC_DMA_ADDR: 899 case GA_CDC_DMA_ADDR:
893 cdd_run(cd, m68k->cycles); 900 cdd_run(cd, m68k->cycles);
894 cd->gate_array[reg] = value; 901 cd->gate_array[reg] = value;
895 cd->cdc_dst_low = 0; 902 cd->cdc_dst_low = 0;
896 //TODO: Confirm if DSR is cleared here on hardware
897 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR;
898 break; 903 break;
899 case GA_STOP_WATCH: 904 case GA_STOP_WATCH:
900 //docs say you should only write zero to reset 905 //docs say you should only write zero to reset
901 //mcd-verificator comments suggest any value will reset 906 //mcd-verificator comments suggest any value will reset
902 timers_run(cd, m68k->cycles); 907 timers_run(cd, m68k->cycles);