Mercurial > repos > blastem
comparison ym2612.c @ 369:fc820ab1394b
Fix left/right enable default value
author | Mike Pavone <pavone@retrodev.com> |
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date | Fri, 31 May 2013 21:30:11 -0700 |
parents | 3ba3b6656fff |
children | 5f215603d001 |
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368:c9d2a2371f5e | 369:fc820ab1394b |
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92 context->buffer_inc = (double)sample_rate / (double)(clock_rate/OP_UPDATE_PERIOD); | 92 context->buffer_inc = (double)sample_rate / (double)(clock_rate/OP_UPDATE_PERIOD); |
93 context->sample_limit = sample_limit*2; | 93 context->sample_limit = sample_limit*2; |
94 for (int i = 0; i < NUM_OPERATORS; i++) { | 94 for (int i = 0; i < NUM_OPERATORS; i++) { |
95 context->operators[i].envelope = MAX_ENVELOPE; | 95 context->operators[i].envelope = MAX_ENVELOPE; |
96 context->operators[i].env_phase = PHASE_RELEASE; | 96 context->operators[i].env_phase = PHASE_RELEASE; |
97 } | |
98 //some games seem to expect that the LR flags start out as 1 | |
99 for (int i = 0; i < NUM_CHANNELS; i++) { | |
100 context->channels[i].lr = 0xC0; | |
97 } | 101 } |
98 if (!did_tbl_init) { | 102 if (!did_tbl_init) { |
99 //populate sine table | 103 //populate sine table |
100 for (int32_t i = 0; i < 512; i++) { | 104 for (int32_t i = 0; i < 512; i++) { |
101 double sine = sin( ((double)(i*2+1) / SINE_TABLE_SIZE) * M_PI_2 ); | 105 double sine = sin( ((double)(i*2+1) / SINE_TABLE_SIZE) * M_PI_2 ); |
476 break; | 480 break; |
477 } | 481 } |
478 case REG_DAC: | 482 case REG_DAC: |
479 if (context->dac_enable) { | 483 if (context->dac_enable) { |
480 context->channels[5].output = (((int16_t)value) - 0x80) << 6; | 484 context->channels[5].output = (((int16_t)value) - 0x80) << 6; |
481 //printf("DAC Write %X(%d)\n", context->channels[5].output, context->channels[5].output); | 485 //printf("DAC Write %X(%d)\n", value, context->channels[5].output); |
482 } | 486 } |
483 break; | 487 break; |
484 case REG_DAC_ENABLE: | 488 case REG_DAC_ENABLE: |
485 //printf("DAC Enable: %X\n", value); | 489 //printf("DAC Enable: %X\n", value); |
486 context->dac_enable = value & 0x80; | 490 context->dac_enable = value & 0x80; |
565 break; | 569 break; |
566 case REG_LR_AMS_PMS: | 570 case REG_LR_AMS_PMS: |
567 context->channels[channel].pms = value & 0x7; | 571 context->channels[channel].pms = value & 0x7; |
568 context->channels[channel].ams = value >> 4 & 0x3; | 572 context->channels[channel].ams = value >> 4 & 0x3; |
569 context->channels[channel].lr = value & 0xC0; | 573 context->channels[channel].lr = value & 0xC0; |
574 //printf("Write of %X to LR_AMS_PMS reg for channel %d\n", value, channel); | |
570 break; | 575 break; |
571 } | 576 } |
572 } | 577 } |
573 } | 578 } |
574 | 579 |
575 context->write_cycle = context->current_cycle; | 580 context->write_cycle = context->current_cycle; |
576 context->selected_reg = 0;//TODO: Verify this | |
577 } | 581 } |
578 | 582 |
579 uint8_t ym_read_status(ym2612_context * context) | 583 uint8_t ym_read_status(ym2612_context * context) |
580 { | 584 { |
581 return context->status; | 585 return context->status; |