Mercurial > repos > blastem
comparison vdp.c @ 474:e128e55710bd
Remove read pending stuff, that had been added in an attempt to fix CRAM/VSRAM undefined bit results. Set number of bits actually saved in VSRAM to 11
author | Mike Pavone <pavone@retrodev.com> |
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date | Sun, 15 Sep 2013 23:33:24 -0700 |
parents | 1358045c0bdd |
children | 50e0cb475294 |
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473:1358045c0bdd | 474:e128e55710bd |
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397 #define DMA_START 0x20 | 397 #define DMA_START 0x20 |
398 | 398 |
399 void external_slot(vdp_context * context) | 399 void external_slot(vdp_context * context) |
400 { | 400 { |
401 fifo_entry * start = context->fifo + context->fifo_read; | 401 fifo_entry * start = context->fifo + context->fifo_read; |
402 if (context->flags2 & FLAG2_READ_PENDING) { | 402 /*if (context->flags2 & FLAG2_READ_PENDING) { |
403 context->flags2 &= ~FLAG2_READ_PENDING; | 403 context->flags2 &= ~FLAG2_READ_PENDING; |
404 context->flags |= FLAG_UNUSED_SLOT; | 404 context->flags |= FLAG_UNUSED_SLOT; |
405 return; | 405 return; |
406 } | 406 }*/ |
407 if (context->fifo_read >= 0 && start->cycle <= context->cycles) { | 407 if (context->fifo_read >= 0 && start->cycle <= context->cycles) { |
408 switch (start->cd & 0xF) | 408 switch (start->cd & 0xF) |
409 { | 409 { |
410 case VRAM_WRITE: | 410 case VRAM_WRITE: |
411 if (start->partial) { | 411 if (start->partial) { |
1572 //TODO: Sprite overflow, sprite collision, odd frame flag | 1572 //TODO: Sprite overflow, sprite collision, odd frame flag |
1573 return value; | 1573 return value; |
1574 } | 1574 } |
1575 | 1575 |
1576 #define CRAM_BITS 0xEEE | 1576 #define CRAM_BITS 0xEEE |
1577 #define VSRAM_BITS 0x3FF | 1577 #define VSRAM_BITS 0x7FF |
1578 #define VSRAM_DIRTY_BITS 0xF800 | 1578 #define VSRAM_DIRTY_BITS 0xF800 |
1579 | 1579 |
1580 uint16_t vdp_data_port_read(vdp_context * context) | 1580 uint16_t vdp_data_port_read(vdp_context * context) |
1581 { | 1581 { |
1582 context->flags &= ~FLAG_PENDING; | 1582 context->flags &= ~FLAG_PENDING; |
1583 if (context->cd & 1) { | 1583 if (context->cd & 1) { |
1584 return 0; | 1584 return 0; |
1585 } | 1585 } |
1586 //Not sure if the FIFO should be drained before processing a read or not, but it would make sense | 1586 //Not sure if the FIFO should be drained before processing a read or not, but it would make sense |
1587 context->flags &= ~FLAG_UNUSED_SLOT; | 1587 context->flags &= ~FLAG_UNUSED_SLOT; |
1588 context->flags2 |= FLAG2_READ_PENDING; | 1588 //context->flags2 |= FLAG2_READ_PENDING; |
1589 while (!(context->flags & FLAG_UNUSED_SLOT)) { | 1589 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
1590 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); | 1590 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
1591 } | 1591 } |
1592 uint16_t value = 0; | 1592 uint16_t value = 0; |
1593 switch (context->cd & 0xF) | 1593 switch (context->cd & 0xF) |