Mercurial > repos > blastem
comparison vdp.c @ 331:de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
author | Mike Pavone <pavone@retrodev.com> |
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date | Tue, 14 May 2013 00:03:26 -0700 |
parents | 57453d3d8be4 |
children | 671a5be51522 |
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330:57453d3d8be4 | 331:de17e0352f27 |
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34 #define SCROLL_BUFFER_SIZE 32 | 34 #define SCROLL_BUFFER_SIZE 32 |
35 #define SCROLL_BUFFER_DRAW 16 | 35 #define SCROLL_BUFFER_DRAW 16 |
36 | 36 |
37 #define FIFO_SIZE 4 | 37 #define FIFO_SIZE 4 |
38 | 38 |
39 #define VINT_SLOTS_H40 (21+16+10) //21 slots before HSYNC, 16 during, 10 after TODO: deal with clock switching during HSYNC | |
40 #define VINT_SLOTS_H32 (33+20+7) //33 slots before HSYNC, 20 during, 7 after TODO: confirm final number | |
41 #define MCLKS_SLOT_H40 16 | 39 #define MCLKS_SLOT_H40 16 |
42 #define MCLKS_SLOT_H32 20 | 40 #define MCLKS_SLOT_H32 20 |
41 #define VINT_CYCLE_H40 (21*MCLKS_SLOT_H40+332+9*MCLKS_SLOT_H40) //21 slots before HSYNC, 16 during, 10 after | |
42 #define VINT_CYCLE_H32 ((33+20+7)*MCLKS_SLOT_H32) //33 slots before HSYNC, 20 during, 7 after TODO: confirm final number | |
43 #define HSYNC_SLOT_H40 21 | 43 #define HSYNC_SLOT_H40 21 |
44 #define MCLK_WEIRD_END (HSYNC_SLOT_H40*MCLKS_SLOT_H40 + 332) | 44 #define MCLK_WEIRD_END (HSYNC_SLOT_H40*MCLKS_SLOT_H40 + 332) |
45 #define SLOT_WEIRD_END (HSYNC_SLOT_H40+17) | 45 #define SLOT_WEIRD_END (HSYNC_SLOT_H40+17) |
46 #define HSYNC_END_H32 (33 * MCLKS_SLOT_H32) | |
47 #define HBLANK_CLEAR_H40 (MCLK_WEIRD_END+61*4) | |
48 #define HBLANK_CLEAR_H32 (HSYNC_END_H32 + 46*5) | |
46 | 49 |
47 void init_vdp_context(vdp_context * context) | 50 void init_vdp_context(vdp_context * context) |
48 { | 51 { |
49 memset(context, 0, sizeof(*context)); | 52 memset(context, 0, sizeof(*context)); |
50 context->vdpmem = malloc(VRAM_SIZE); | 53 context->vdpmem = malloc(VRAM_SIZE); |
1120 } else { | 1123 } else { |
1121 context->flags2 |= FLAG2_HINT_PENDING; | 1124 context->flags2 |= FLAG2_HINT_PENDING; |
1122 context->hint_counter = context->regs[REG_HINT]; | 1125 context->hint_counter = context->regs[REG_HINT]; |
1123 } | 1126 } |
1124 } else if(line == active_lines) { | 1127 } else if(line == active_lines) { |
1125 uint32_t intcyc = context->latched_mode & BIT_H40 ? VINT_SLOTS_H40 * MCLKS_SLOT_H40 : VINT_SLOTS_H32 * MCLKS_SLOT_H32; | 1128 uint32_t intcyc = context->latched_mode & BIT_H40 ? VINT_CYCLE_H40 : VINT_CYCLE_H32; |
1126 if (linecyc == intcyc) { | 1129 if (linecyc == intcyc) { |
1127 context->flags2 |= FLAG2_VINT_PENDING; | 1130 context->flags2 |= FLAG2_VINT_PENDING; |
1128 } | 1131 } |
1129 } | 1132 } |
1130 uint32_t inccycles, slot; | 1133 uint32_t inccycles, slot; |
1362 uint32_t line= context->cycles / MCLKS_LINE; | 1365 uint32_t line= context->cycles / MCLKS_LINE; |
1363 uint32_t linecyc = context->cycles % MCLKS_LINE; | 1366 uint32_t linecyc = context->cycles % MCLKS_LINE; |
1364 if (line >= (context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE)) { | 1367 if (line >= (context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE)) { |
1365 value |= 0x8; | 1368 value |= 0x8; |
1366 } | 1369 } |
1367 if (linecyc < (context->latched_mode & BIT_H40 ? (148 + 61) * 4 : ( + 46) * 5)) { | 1370 if (linecyc < (context->latched_mode & BIT_H40 ? HBLANK_CLEAR_H40 : HBLANK_CLEAR_H32)) { |
1368 value |= 0x4; | 1371 value |= 0x4; |
1369 } | 1372 } |
1370 if (context->flags & FLAG_DMA_RUN) { | 1373 if (context->flags & FLAG_DMA_RUN) { |
1371 value |= 0x2; | 1374 value |= 0x2; |
1372 } | 1375 } |
1483 return hcycle; | 1486 return hcycle; |
1484 } | 1487 } |
1485 | 1488 |
1486 uint32_t vdp_next_vint(vdp_context * context) | 1489 uint32_t vdp_next_vint(vdp_context * context) |
1487 { | 1490 { |
1488 //TODO: deal with clock adjustemnts handled in vdp_run_context | |
1489 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) { | 1491 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) { |
1490 return 0xFFFFFFFF; | 1492 return 0xFFFFFFFF; |
1491 } | 1493 } |
1492 if (context->flags2 & FLAG2_VINT_PENDING) { | 1494 if (context->flags2 & FLAG2_VINT_PENDING) { |
1493 return context->cycles; | 1495 return context->cycles; |
1494 } | 1496 } |
1495 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; | 1497 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
1496 uint32_t vcycle = MCLKS_LINE * active_lines; | 1498 uint32_t vcycle = MCLKS_LINE * active_lines; |
1497 if (context->latched_mode & BIT_H40) { | 1499 if (context->latched_mode & BIT_H40) { |
1498 vcycle += VINT_SLOTS_H40 * MCLKS_SLOT_H40; | 1500 vcycle += VINT_CYCLE_H40; |
1499 } else { | 1501 } else { |
1500 vcycle += VINT_SLOTS_H32 * MCLKS_SLOT_H32; | 1502 vcycle += VINT_CYCLE_H32; |
1501 } | 1503 } |
1502 if (vcycle < context->cycles) { | 1504 if (vcycle < context->cycles) { |
1503 return 0xFFFFFFFF; | 1505 return 0xFFFFFFFF; |
1504 } | 1506 } |
1505 return vcycle; | 1507 return vcycle; |