Mercurial > repos > blastem
comparison lc8951.c @ 2131:d90d92ce5cab
Improve CDC decode timing accuracy
author | Michael Pavone <pavone@retrodev.com> |
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date | Wed, 16 Mar 2022 00:16:36 -0700 |
parents | 28b6453cf7e3 |
children | d9151d0894c7 |
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2130:28b6453cf7e3 | 2131:d90d92ce5cab |
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274 { | 274 { |
275 lc8951_run(context, cycle); | 275 lc8951_run(context, cycle); |
276 uint16_t current_write_addr = context->regs[WAL] | (context->regs[WAH] << 8); | 276 uint16_t current_write_addr = context->regs[WAL] | (context->regs[WAH] << 8); |
277 | 277 |
278 context->sector_counter++; | 278 context->sector_counter++; |
279 context->sector_counter &= 0xFFF; | |
279 uint8_t sync_detected = 0, sync_ignored = 0; | 280 uint8_t sync_detected = 0, sync_ignored = 0; |
280 if (byte == 0) { | 281 if (byte == 0) { |
281 if (context->sync_counter == 11 && ((sector_offset & 3) == 3)) { | 282 if (context->sync_counter == 11 && ((sector_offset & 3) == 3)) { |
282 if (context->ctrl1 & BIT_SYDEN) { | 283 if (context->ctrl1 & BIT_SYDEN) { |
283 sync_detected = 1; | 284 sync_detected = 1; |
319 uint16_t block_start = current_write_addr + 1 - 2352; | 320 uint16_t block_start = current_write_addr + 1 - 2352; |
320 context->regs[PTL] = block_start; | 321 context->regs[PTL] = block_start; |
321 context->regs[PTH] = block_start >> 8; | 322 context->regs[PTH] = block_start >> 8; |
322 } | 323 } |
323 printf("Decoding block starting at %X (WRRQ: %d)\n", context->regs[PTL] | (context->regs[PTH] << 8), !!(context->ctrl0 & BIT_WRRQ)); | 324 printf("Decoding block starting at %X (WRRQ: %d)\n", context->regs[PTL] | (context->regs[PTH] << 8), !!(context->ctrl0 & BIT_WRRQ)); |
324 //TODO: Datasheet has some hints about how long decoding takes in the form of how long DECI is asserted | 325 //Based on measurements of a Wondermega M1 (LC8951) with SYDEN, SYIEN and DECEN only |
325 context->decode_end = context->cycle + 2352 * context->clock_step * 4; | 326 context->decode_end = context->cycle + 22030 * context->clock_step; |
326 } | 327 } |
327 } else { | 328 } else { |
328 if (sync_ignored) { | 329 if (sync_ignored) { |
329 context->regs[STAT0] |= BIT_SBLK; | 330 context->regs[STAT0] |= BIT_SBLK; |
330 } | 331 } |
353 if ((~context->regs[IFSTAT]) & context->ifctrl & (BIT_CMDI|BIT_DTEI|BIT_DECI)) { | 354 if ((~context->regs[IFSTAT]) & context->ifctrl & (BIT_CMDI|BIT_DTEI|BIT_DECI)) { |
354 //interrupt already pending | 355 //interrupt already pending |
355 return context->cycle; | 356 return context->cycle; |
356 } | 357 } |
357 uint32_t deci_cycle = CYCLE_NEVER; | 358 uint32_t deci_cycle = CYCLE_NEVER; |
358 if (context->ifctrl & BIT_DECI) { | 359 if (context->ifctrl & BIT_DECIEN) { |
359 deci_cycle = context->decode_end; | 360 deci_cycle = context->decode_end; |
360 } | 361 } |
361 uint32_t dtei_cycle = CYCLE_NEVER; | 362 uint32_t dtei_cycle = CYCLE_NEVER; |
362 if (context->ifctrl & BIT_DTEI) { | 363 if (context->ifctrl & BIT_DTEIEN) { |
363 dtei_cycle = context->transfer_end; | 364 dtei_cycle = context->transfer_end; |
364 } | 365 } |
365 return deci_cycle < dtei_cycle ? deci_cycle : dtei_cycle; | 366 return deci_cycle < dtei_cycle ? deci_cycle : dtei_cycle; |
366 } | 367 } |
367 | 368 |