Mercurial > repos > blastem
comparison m68k_core_x86.c @ 989:d70000fdff0b
Implemented IR and undefined bits of info word for address error exception frames
author | Michael Pavone <pavone@retrodev.com> |
---|---|
date | Wed, 27 Apr 2016 21:39:17 -0700 |
parents | 1f09994e92c5 |
children | 33a46d35b913 |
comparison
equal
deleted
inserted
replaced
988:ce9df7a5fdf2 | 989:d70000fdff0b |
---|---|
2143 call(code, opts->get_sr); | 2143 call(code, opts->get_sr); |
2144 areg_to_native(opts, 7, opts->gen.scratch2); | 2144 areg_to_native(opts, 7, opts->gen.scratch2); |
2145 call(code, opts->write_16); | 2145 call(code, opts->write_16); |
2146 //save instruction register | 2146 //save instruction register |
2147 subi_areg(opts, 2, 7); | 2147 subi_areg(opts, 2, 7); |
2148 //TODO: Use actual value | 2148 //calculate IR |
2149 mov_ir(code, 0, opts->gen.scratch1, SZ_W); | 2149 push_r(code, opts->gen.context_reg); |
2150 call(code, opts->gen.save_context); | |
2151 call_args_abi(code, (code_ptr)m68k_get_ir, 1, opts->gen.context_reg); | |
2152 mov_rr(code, RAX, opts->gen.scratch1, SZ_W); | |
2153 pop_r(code, opts->gen.context_reg); | |
2154 push_r(code, RAX); //save it for use in the "info" word | |
2155 call(code, opts->gen.load_context); | |
2156 //write it to the stack | |
2150 areg_to_native(opts, 7, opts->gen.scratch2); | 2157 areg_to_native(opts, 7, opts->gen.scratch2); |
2151 call(code, opts->write_16); | 2158 call(code, opts->write_16); |
2152 //save access address | 2159 //save access address |
2153 subi_areg(opts, 4, 7); | 2160 subi_areg(opts, 4, 7); |
2154 mov_ir(code, inst->address, opts->gen.scratch1, SZ_D); | 2161 mov_ir(code, inst->address, opts->gen.scratch1, SZ_D); |
2160 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, status), opts->gen.scratch1, SZ_B); | 2167 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, status), opts->gen.scratch1, SZ_B); |
2161 shr_ir(code, 3, opts->gen.scratch1, SZ_B); | 2168 shr_ir(code, 3, opts->gen.scratch1, SZ_B); |
2162 and_ir(code, 4, opts->gen.scratch1, SZ_B); | 2169 and_ir(code, 4, opts->gen.scratch1, SZ_B); |
2163 //set FC1 to one to indicate instruction fetch, and R/W to indicate read | 2170 //set FC1 to one to indicate instruction fetch, and R/W to indicate read |
2164 or_ir(code, 0x12, opts->gen.scratch1, SZ_B); | 2171 or_ir(code, 0x12, opts->gen.scratch1, SZ_B); |
2165 //TODO: Figure out what undefined bits get set to, looks like it might be value of IR | 2172 //set undefined bits to IR value |
2173 pop_r(code, opts->gen.scratch2); | |
2174 and_ir(code, 0xFFE0, opts->gen.scratch2, SZ_W); | |
2175 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W); | |
2166 subi_areg(opts, 2, 7); | 2176 subi_areg(opts, 2, 7); |
2167 areg_to_native(opts, 7, opts->gen.scratch2); | 2177 areg_to_native(opts, 7, opts->gen.scratch2); |
2168 call(code, opts->write_16); | 2178 call(code, opts->write_16); |
2169 //set supervisor bit | 2179 //set supervisor bit |
2170 or_irdisp(code, 0x20, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); | 2180 or_irdisp(code, 0x20, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); |
2569 call(code, opts->get_sr); | 2579 call(code, opts->get_sr); |
2570 areg_to_native(opts, 7, opts->gen.scratch2); | 2580 areg_to_native(opts, 7, opts->gen.scratch2); |
2571 call(code, opts->write_16); | 2581 call(code, opts->write_16); |
2572 //save instruction register | 2582 //save instruction register |
2573 subi_areg(opts, 2, 7); | 2583 subi_areg(opts, 2, 7); |
2574 //TODO: Use actual value | 2584 //calculate IR |
2575 mov_ir(code, 0, opts->gen.scratch1, SZ_W); | 2585 push_r(code, opts->gen.context_reg); |
2586 call(code, opts->gen.save_context); | |
2587 call_args_abi(code, (code_ptr)m68k_get_ir, 1, opts->gen.context_reg); | |
2588 mov_rr(code, RAX, opts->gen.scratch1, SZ_W); | |
2589 pop_r(code, opts->gen.context_reg); | |
2590 pop_r(code, opts->gen.scratch2); //access address | |
2591 push_r(code, RAX); //save it for use in the "info" word | |
2592 push_r(code, opts->gen.scratch2); //access address | |
2593 call(code, opts->gen.load_context); | |
2594 //write it to the stack | |
2576 areg_to_native(opts, 7, opts->gen.scratch2); | 2595 areg_to_native(opts, 7, opts->gen.scratch2); |
2577 call(code, opts->write_16); | 2596 call(code, opts->write_16); |
2578 //save access address | 2597 //save access address |
2579 subi_areg(opts, 4, 7); | 2598 subi_areg(opts, 4, 7); |
2580 pop_r(code, opts->gen.scratch1); | 2599 pop_r(code, opts->gen.scratch1); |
2586 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, status), opts->gen.scratch1, SZ_B); | 2605 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, status), opts->gen.scratch1, SZ_B); |
2587 shr_ir(code, 3, opts->gen.scratch1, SZ_B); | 2606 shr_ir(code, 3, opts->gen.scratch1, SZ_B); |
2588 and_ir(code, 4, opts->gen.scratch1, SZ_B); | 2607 and_ir(code, 4, opts->gen.scratch1, SZ_B); |
2589 //set FC0 to one to indicate data access | 2608 //set FC0 to one to indicate data access |
2590 or_ir(code, 1, opts->gen.scratch1, SZ_B); | 2609 or_ir(code, 1, opts->gen.scratch1, SZ_B); |
2591 //TODO: Figure out what undefined bits get set to, looks like it might be value of IR | 2610 //set undefined bits to IR value |
2611 pop_r(code, opts->gen.scratch2); | |
2612 and_ir(code, 0xFFE0, opts->gen.scratch2, SZ_W); | |
2613 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W); | |
2592 subi_areg(opts, 2, 7); | 2614 subi_areg(opts, 2, 7); |
2593 areg_to_native(opts, 7, opts->gen.scratch2); | 2615 areg_to_native(opts, 7, opts->gen.scratch2); |
2594 call(code, opts->write_16); | 2616 call(code, opts->write_16); |
2595 //set supervisor bit | 2617 //set supervisor bit |
2596 or_irdisp(code, 0x20, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); | 2618 or_irdisp(code, 0x20, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); |
2619 call(code, opts->get_sr); | 2641 call(code, opts->get_sr); |
2620 areg_to_native(opts, 7, opts->gen.scratch2); | 2642 areg_to_native(opts, 7, opts->gen.scratch2); |
2621 call(code, opts->write_16); | 2643 call(code, opts->write_16); |
2622 //save instruction register | 2644 //save instruction register |
2623 subi_areg(opts, 2, 7); | 2645 subi_areg(opts, 2, 7); |
2624 //TODO: Use actual value | 2646 //calculate IR |
2625 mov_ir(code, 0, opts->gen.scratch1, SZ_W); | 2647 push_r(code, opts->gen.context_reg); |
2648 call(code, opts->gen.save_context); | |
2649 call_args_abi(code, (code_ptr)m68k_get_ir, 1, opts->gen.context_reg); | |
2650 mov_rr(code, RAX, opts->gen.scratch1, SZ_W); | |
2651 pop_r(code, opts->gen.context_reg); | |
2652 pop_r(code, opts->gen.scratch2); //access address | |
2653 push_r(code, RAX); //save it for use in the "info" word | |
2654 push_r(code, opts->gen.scratch2); //access address | |
2655 call(code, opts->gen.load_context); | |
2656 //write it to the stack | |
2626 areg_to_native(opts, 7, opts->gen.scratch2); | 2657 areg_to_native(opts, 7, opts->gen.scratch2); |
2627 call(code, opts->write_16); | 2658 call(code, opts->write_16); |
2628 //save access address | 2659 //save access address |
2629 subi_areg(opts, 4, 7); | 2660 subi_areg(opts, 4, 7); |
2630 pop_r(code, opts->gen.scratch1); | 2661 pop_r(code, opts->gen.scratch1); |
2636 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, status), opts->gen.scratch1, SZ_B); | 2667 mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, status), opts->gen.scratch1, SZ_B); |
2637 shr_ir(code, 3, opts->gen.scratch1, SZ_B); | 2668 shr_ir(code, 3, opts->gen.scratch1, SZ_B); |
2638 and_ir(code, 4, opts->gen.scratch1, SZ_B); | 2669 and_ir(code, 4, opts->gen.scratch1, SZ_B); |
2639 //set FC0 to one to indicate data access, and R/W to indicate read | 2670 //set FC0 to one to indicate data access, and R/W to indicate read |
2640 or_ir(code, 0x11, opts->gen.scratch1, SZ_B); | 2671 or_ir(code, 0x11, opts->gen.scratch1, SZ_B); |
2641 //TODO: Figure out what undefined bits get set to, looks like it might be value of IR | 2672 //set undefined bits to IR value |
2673 pop_r(code, opts->gen.scratch2); | |
2674 and_ir(code, 0xFFE0, opts->gen.scratch2, SZ_W); | |
2675 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W); | |
2642 subi_areg(opts, 2, 7); | 2676 subi_areg(opts, 2, 7); |
2643 areg_to_native(opts, 7, opts->gen.scratch2); | 2677 areg_to_native(opts, 7, opts->gen.scratch2); |
2644 call(code, opts->write_16); | 2678 call(code, opts->write_16); |
2645 //set supervisor bit | 2679 //set supervisor bit |
2646 or_irdisp(code, 0x20, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); | 2680 or_irdisp(code, 0x20, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B); |