Mercurial > repos > blastem
comparison m68k_to_x86.c @ 49:d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
author | Mike Pavone <pavone@retrodev.com> |
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date | Wed, 12 Dec 2012 23:21:11 -0800 |
parents | f2aaaf36c875 |
children | 937b47c9b79b |
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48:0bdda50c7364 | 49:d2e43d64e999 |
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687 dst = setcc_r(dst, CC_Z, FLAG_Z); | 687 dst = setcc_r(dst, CC_Z, FLAG_Z); |
688 dst = setcc_r(dst, CC_S, FLAG_N); | 688 dst = setcc_r(dst, CC_S, FLAG_N); |
689 dst = setcc_r(dst, CC_O, FLAG_V); | 689 dst = setcc_r(dst, CC_O, FLAG_V); |
690 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); | 690 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
691 dst = check_cycles(dst); | 691 dst = check_cycles(dst); |
692 dst = m68k_save_result(inst, dst, opts); | |
692 break; | 693 break; |
693 case M68K_ADDX: | 694 case M68K_ADDX: |
695 break; | |
694 case M68K_AND: | 696 case M68K_AND: |
697 dst = cycles(dst, BUS); | |
698 if (src_op.mode == MODE_REG_DIRECT) { | |
699 if (dst_op.mode == MODE_REG_DIRECT) { | |
700 dst = and_rr(dst, src_op.base, dst_op.base, inst->extra.size); | |
701 } else { | |
702 dst = and_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); | |
703 } | |
704 } else if (src_op.mode == MODE_REG_DISPLACE8) { | |
705 dst = and_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); | |
706 } else { | |
707 if (dst_op.mode == MODE_REG_DIRECT) { | |
708 dst = and_ir(dst, src_op.disp, dst_op.base, inst->extra.size); | |
709 } else { | |
710 dst = and_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); | |
711 } | |
712 } | |
713 dst = mov_ir(dst, 0, FLAG_C, SZ_B); | |
714 dst = setcc_r(dst, CC_Z, FLAG_Z); | |
715 dst = setcc_r(dst, CC_S, FLAG_N); | |
716 dst = mov_ir(dst, 0, FLAG_V, SZ_B); | |
717 dst = check_cycles(dst); | |
718 dst = m68k_save_result(inst, dst, opts); | |
719 break; | |
695 case M68K_ANDI_CCR: | 720 case M68K_ANDI_CCR: |
696 case M68K_ANDI_SR: | 721 case M68K_ANDI_SR: |
697 case M68K_ASL: | 722 case M68K_ASL: |
723 case M68K_LSL: | |
698 case M68K_ASR: | 724 case M68K_ASR: |
699 case M68K_BCC: | 725 case M68K_LSR: |
700 case M68K_BCHG: | 726 case M68K_BCHG: |
701 case M68K_BCLR: | 727 case M68K_BCLR: |
702 case M68K_BSET: | 728 case M68K_BSET: |
703 case M68K_BSR: | |
704 case M68K_BTST: | 729 case M68K_BTST: |
705 case M68K_CHK: | 730 case M68K_CHK: |
706 case M68K_CLR: | 731 case M68K_CLR: |
732 break; | |
707 case M68K_CMP: | 733 case M68K_CMP: |
708 dst = cycles(dst, BUS); | 734 dst = cycles(dst, BUS); |
709 if (src_op.mode == MODE_REG_DIRECT) { | 735 if (src_op.mode == MODE_REG_DIRECT) { |
710 if (dst_op.mode == MODE_REG_DIRECT) { | 736 if (dst_op.mode == MODE_REG_DIRECT) { |
711 dst = cmp_rr(dst, src_op.base, dst_op.base, inst->extra.size); | 737 dst = cmp_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
725 dst = setcc_r(dst, CC_Z, FLAG_Z); | 751 dst = setcc_r(dst, CC_Z, FLAG_Z); |
726 dst = setcc_r(dst, CC_S, FLAG_N); | 752 dst = setcc_r(dst, CC_S, FLAG_N); |
727 dst = setcc_r(dst, CC_O, FLAG_V); | 753 dst = setcc_r(dst, CC_O, FLAG_V); |
728 dst = check_cycles(dst); | 754 dst = check_cycles(dst); |
729 break; | 755 break; |
730 case M68K_DBCC: | |
731 case M68K_DIVS: | 756 case M68K_DIVS: |
732 case M68K_DIVU: | 757 case M68K_DIVU: |
758 break; | |
733 case M68K_EOR: | 759 case M68K_EOR: |
760 dst = cycles(dst, BUS); | |
761 if (src_op.mode == MODE_REG_DIRECT) { | |
762 if (dst_op.mode == MODE_REG_DIRECT) { | |
763 dst = xor_rr(dst, src_op.base, dst_op.base, inst->extra.size); | |
764 } else { | |
765 dst = xor_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); | |
766 } | |
767 } else if (src_op.mode == MODE_REG_DISPLACE8) { | |
768 dst = xor_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); | |
769 } else { | |
770 if (dst_op.mode == MODE_REG_DIRECT) { | |
771 dst = xor_ir(dst, src_op.disp, dst_op.base, inst->extra.size); | |
772 } else { | |
773 dst = xor_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); | |
774 } | |
775 } | |
776 dst = mov_ir(dst, 0, FLAG_C, SZ_B); | |
777 dst = setcc_r(dst, CC_Z, FLAG_Z); | |
778 dst = setcc_r(dst, CC_S, FLAG_N); | |
779 dst = mov_ir(dst, 0, FLAG_V, SZ_B); | |
780 dst = check_cycles(dst); | |
781 dst = m68k_save_result(inst, dst, opts); | |
782 break; | |
734 case M68K_EORI_CCR: | 783 case M68K_EORI_CCR: |
735 case M68K_EORI_SR: | 784 case M68K_EORI_SR: |
736 case M68K_EXG: | 785 case M68K_EXG: |
737 dst = cycles(dst, 6); | 786 dst = cycles(dst, 6); |
738 if (dst_op.mode == MODE_REG_DIRECT) { | 787 if (dst_op.mode == MODE_REG_DIRECT) { |
756 } | 805 } |
757 } | 806 } |
758 dst = check_cycles(dst); | 807 dst = check_cycles(dst); |
759 break; | 808 break; |
760 case M68K_EXT: | 809 case M68K_EXT: |
810 break; | |
761 case M68K_ILLEGAL: | 811 case M68K_ILLEGAL: |
762 dst = call(dst, (uint8_t *)m68k_save_context); | 812 dst = call(dst, (uint8_t *)m68k_save_context); |
763 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); | 813 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
764 dst = call(dst, (uint8_t *)print_regs_exit); | 814 dst = call(dst, (uint8_t *)print_regs_exit); |
765 break; | 815 break; |
766 case M68K_JMP: | 816 case M68K_JMP: |
767 case M68K_JSR: | 817 case M68K_JSR: |
768 case M68K_LEA: | 818 case M68K_LEA: |
769 case M68K_LINK: | 819 case M68K_LINK: |
770 case M68K_LSL: | |
771 case M68K_LSR: | |
772 case M68K_MOVE_CCR: | 820 case M68K_MOVE_CCR: |
773 case M68K_MOVE_FROM_SR: | 821 case M68K_MOVE_FROM_SR: |
774 case M68K_MOVE_SR: | 822 case M68K_MOVE_SR: |
775 case M68K_MOVE_USP: | 823 case M68K_MOVE_USP: |
776 case M68K_MOVEM: | 824 case M68K_MOVEM: |
778 case M68K_MULS: | 826 case M68K_MULS: |
779 case M68K_MULU: | 827 case M68K_MULU: |
780 case M68K_NBCD: | 828 case M68K_NBCD: |
781 case M68K_NEG: | 829 case M68K_NEG: |
782 case M68K_NEGX: | 830 case M68K_NEGX: |
831 break; | |
783 case M68K_NOP: | 832 case M68K_NOP: |
833 dst = cycles(dst, BUS); | |
834 dst = check_cycles(dst); | |
835 break; | |
784 case M68K_NOT: | 836 case M68K_NOT: |
837 break; | |
785 case M68K_OR: | 838 case M68K_OR: |
839 dst = cycles(dst, BUS); | |
840 if (src_op.mode == MODE_REG_DIRECT) { | |
841 if (dst_op.mode == MODE_REG_DIRECT) { | |
842 dst = or_rr(dst, src_op.base, dst_op.base, inst->extra.size); | |
843 } else { | |
844 dst = or_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); | |
845 } | |
846 } else if (src_op.mode == MODE_REG_DISPLACE8) { | |
847 dst = or_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); | |
848 } else { | |
849 if (dst_op.mode == MODE_REG_DIRECT) { | |
850 dst = or_ir(dst, src_op.disp, dst_op.base, inst->extra.size); | |
851 } else { | |
852 dst = or_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); | |
853 } | |
854 } | |
855 dst = mov_ir(dst, 0, FLAG_C, SZ_B); | |
856 dst = setcc_r(dst, CC_Z, FLAG_Z); | |
857 dst = setcc_r(dst, CC_S, FLAG_N); | |
858 dst = mov_ir(dst, 0, FLAG_V, SZ_B); | |
859 dst = check_cycles(dst); | |
860 dst = m68k_save_result(inst, dst, opts); | |
861 break; | |
786 case M68K_ORI_CCR: | 862 case M68K_ORI_CCR: |
787 case M68K_ORI_SR: | 863 case M68K_ORI_SR: |
788 case M68K_PEA: | 864 case M68K_PEA: |
789 case M68K_RESET: | 865 case M68K_RESET: |
790 case M68K_ROL: | 866 case M68K_ROL: |
791 case M68K_ROR: | 867 case M68K_ROR: |
792 case M68K_ROXL: | 868 case M68K_ROXL: |
793 case M68K_ROXR: | 869 case M68K_ROXR: |
794 case M68K_RTE: | 870 case M68K_RTE: |
795 case M68K_RTR: | 871 case M68K_RTR: |
796 case M68K_RTS: | |
797 case M68K_SBCD: | 872 case M68K_SBCD: |
798 case M68K_SCC: | 873 case M68K_SCC: |
799 case M68K_STOP: | 874 case M68K_STOP: |
875 break; | |
800 case M68K_SUB: | 876 case M68K_SUB: |
801 dst = cycles(dst, BUS); | 877 dst = cycles(dst, BUS); |
802 if (src_op.mode == MODE_REG_DIRECT) { | 878 if (src_op.mode == MODE_REG_DIRECT) { |
803 if (dst_op.mode == MODE_REG_DIRECT) { | 879 if (dst_op.mode == MODE_REG_DIRECT) { |
804 dst = sub_rr(dst, src_op.base, dst_op.base, inst->extra.size); | 880 dst = sub_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
818 dst = setcc_r(dst, CC_Z, FLAG_Z); | 894 dst = setcc_r(dst, CC_Z, FLAG_Z); |
819 dst = setcc_r(dst, CC_S, FLAG_N); | 895 dst = setcc_r(dst, CC_S, FLAG_N); |
820 dst = setcc_r(dst, CC_O, FLAG_V); | 896 dst = setcc_r(dst, CC_O, FLAG_V); |
821 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); | 897 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
822 dst = check_cycles(dst); | 898 dst = check_cycles(dst); |
899 dst = m68k_save_result(inst, dst, opts); | |
823 break; | 900 break; |
824 case M68K_SUBX: | 901 case M68K_SUBX: |
902 break; | |
825 case M68K_SWAP: | 903 case M68K_SWAP: |
904 dst = cycles(dst, BUS); | |
905 if (src_op.mode == MODE_REG_DIRECT) { | |
906 dst = rol_ir(dst, 16, src_op.base, inst->extra.size); | |
907 } else{ | |
908 dst = rol_irdisp8(dst, 16, src_op.base, src_op.disp, inst->extra.size); | |
909 } | |
910 dst = mov_ir(dst, 0, FLAG_C, SZ_B); | |
911 dst = setcc_r(dst, CC_Z, FLAG_Z); | |
912 dst = setcc_r(dst, CC_S, FLAG_N); | |
913 dst = mov_ir(dst, 0, FLAG_V, SZ_B); | |
914 dst = check_cycles(dst); | |
915 break; | |
826 case M68K_TAS: | 916 case M68K_TAS: |
827 case M68K_TRAP: | 917 case M68K_TRAP: |
828 case M68K_TRAPV: | 918 case M68K_TRAPV: |
829 case M68K_TST: | 919 case M68K_TST: |
920 dst = cycles(dst, BUS); | |
921 if (src_op.mode == MODE_REG_DIRECT) { | |
922 dst = cmp_ir(dst, 0, src_op.base, inst->extra.size); | |
923 } else { //M68000 doesn't support immedate operand for tst, so this must be MODE_REG_DISPLACE8 | |
924 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, inst->extra.size); | |
925 } | |
926 dst = setcc_r(dst, CC_C, FLAG_C); | |
927 dst = setcc_r(dst, CC_Z, FLAG_Z); | |
928 dst = setcc_r(dst, CC_S, FLAG_N); | |
929 dst = setcc_r(dst, CC_O, FLAG_V); | |
930 dst = check_cycles(dst); | |
931 break; | |
830 case M68K_UNLK: | 932 case M68K_UNLK: |
831 case M68K_INVALID: | 933 case M68K_INVALID: |
832 break; | 934 break; |
833 } | 935 } |
834 return dst; | 936 return dst; |