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Fix some issues in new 68K core and add implementations of negx and clr instructions
author Michael Pavone <pavone@retrodev.com>
date Thu, 15 Feb 2024 21:49:17 -0800
parents 7d4df6b74263
children 6c93869babc1
comparison
equal deleted inserted replaced
2447:414eb8c34198 2448:d1eec03dca09
6 interrupt m68k_interrupt 6 interrupt m68k_interrupt
7 include m68k_util.c 7 include m68k_util.c
8 sync_cycle m68k_sync_cycle 8 sync_cycle m68k_sync_cycle
9 9
10 declare 10 declare
11 typedef m68k_context *(*sync_fun)(m68k_context * context, uint32_t address);
12 typedef m68k_context *(*int_ack_fun)(m68k_context * context);
11 typedef m68k_context *(*m68k_reset_handler)(m68k_context *context); 13 typedef m68k_context *(*m68k_reset_handler)(m68k_context *context);
12 void init_m68k_opts(m68k_options *opts, memmap_chunk * memmap, uint32_t num_chunks, uint32_t clock_divider); 14 void init_m68k_opts(m68k_options *opts, memmap_chunk * memmap, uint32_t num_chunks, uint32_t clock_divider, sync_fun sync_components, int_ack_fun int_ack);
13 m68k_context *init_68k_context(m68k_options * opts, m68k_reset_handler reset_handler); 15 m68k_context *init_68k_context(m68k_options * opts, m68k_reset_handler reset_handler);
14 void m68k_reset(m68k_context *context); 16 void m68k_reset(m68k_context *context);
15 void m68k_print_regs(m68k_context *context); 17 void m68k_print_regs(m68k_context *context);
16 18
17 regs 19 regs
302 m68k_mem_src scratch1 Z isdst 304 m68k_mem_src scratch1 Z isdst
303 305
304 case 6 306 case 6
305 #indexed 307 #indexed
306 m68k_index_word 308 m68k_index_word
309 cycles 2
307 add aregs.reg scratch1 scratch1 310 add aregs.reg scratch1 scratch1
308 311
309 m68k_mem_src scratch1 Z isdst 312 m68k_mem_src scratch1 Z isdst
310 case 7 313 case 7
311 #pc-relative and absolute modes 314 #pc-relative and absolute modes
335 m68k_mem_src scratch1 Z isdst 338 m68k_mem_src scratch1 Z isdst
336 339
337 case 3 340 case 3
338 #pc indexed 341 #pc indexed
339 m68k_index_word 342 m68k_index_word
343 cycles 2
340 add pc scratch1 scratch1 344 add pc scratch1 scratch1
341 sub 2 scratch1 scratch1 345 sub 2 scratch1 scratch1
342 m68k_mem_src scratch1 Z isdst 346 m68k_mem_src scratch1 Z isdst
343 347
344 case 4 348 case 4
483 end 487 end
484 488
485 m68k_fetch_dst_ea M R Z 489 m68k_fetch_dst_ea M R Z
486 switch M 490 switch M
487 case 1 491 case 1
492 cycles 4
488 add src dst dst Z 493 add src dst dst Z
489 default 494 default
490 add src dst dst Z 495 add src dst dst Z
491 update_flags XNZVC 496 update_flags XNZVC
492 end 497 end
870 default 875 default
871 meta shift C 876 meta shift C
872 end 877 end
873 lsr dregs.R shift dregs.R Z 878 lsr dregs.R shift dregs.R Z
874 update_flags XNZV0C 879 update_flags XNZV0C
875 add shift shift shift 880 local cyc 32
876 switch Z 881 cyc = shift + shift
877 case 2 882 switch Z
878 add 4 shift shift 883 case 2
879 default 884 cyc += 4
880 add 2 shift shift 885 default
881 end 886 cyc += 2
882 cycles shift 887 end
888 cycles cyc
883 #TODO: should this happen before or after the majority of the shift? 889 #TODO: should this happen before or after the majority of the shift?
884 m68k_prefetch 890 m68k_prefetch
885 891
886 1110CCC0ZZ101RRR lsr_dn 892 1110CCC0ZZ101RRR lsr_dn
887 invalid Z 3 893 invalid Z 3
1123 invalid M 7 R 5 1129 invalid M 7 R 5
1124 invalid M 7 R 6 1130 invalid M 7 R 6
1125 invalid M 7 R 7 1131 invalid M 7 R 7
1126 m68k_fetch_src_ea M R 1 1132 m68k_fetch_src_ea M R 1
1127 mov scratch1 ccr 1133 mov scratch1 ccr
1134 cycles 8
1128 m68k_prefetch 1135 m68k_prefetch
1129 1136
1130 0100011011MMMRRR move_to_sr 1137 0100011011MMMRRR move_to_sr
1131 invalid M 1 1138 invalid M 1
1132 invalid M 7 R 5 1139 invalid M 7 R 5
1134 invalid M 7 R 7 1141 invalid M 7 R 7
1135 m68k_fetch_src_ea M R 1 1142 m68k_fetch_src_ea M R 1
1136 mov scratch1 ccr 1143 mov scratch1 ccr
1137 lsr scratch1 8 status 1144 lsr scratch1 8 status
1138 update_sync 1145 update_sync
1146 cycles 8
1139 m68k_prefetch 1147 m68k_prefetch
1140 1148
1141 0100000011MMMRRR move_from_sr 1149 0100000011MMMRRR move_from_sr
1142 invalid M 1 1150 invalid M 1
1143 invalid M 7 R 2 1151 invalid M 7 R 2
1148 invalid M 7 R 7 1156 invalid M 7 R 7
1149 m68k_fetch_dst_ea M R 1 1157 m68k_fetch_dst_ea M R 1
1150 lsl status 8 scratch1 1158 lsl status 8 scratch1
1151 or ccr scratch1 scratch1 1159 or ccr scratch1 scratch1
1152 mov scratch1 dst 1160 mov scratch1 dst
1161 if M
1162 cycles 4
1163 else
1164 cycles 2
1165 end
1153 m68k_save_dst 1 1166 m68k_save_dst 1
1154 m68k_prefetch 1167 m68k_prefetch
1155 1168
1169 01000000ZZMMMRRR negx
1170 invalid M 1
1171 invalid M 7 R 2
1172 invalid M 7 R 3
1173 invalid M 7 R 4
1174 invalid M 7 R 5
1175 invalid M 7 R 6
1176 invalid M 7 R 7
1177 m68k_fetch_dst_ea M R Z
1178 sbc dst 0 dst Z
1179 update_flags XNZVC
1180 m68k_save_dst Z
1181 m68k_prefetch
1182
1183 01000010ZZMMMRRR clr
1184 invalid M 1
1185 invalid M 7 R 2
1186 invalid M 7 R 3
1187 invalid M 7 R 4
1188 invalid M 7 R 5
1189 invalid M 7 R 6
1190 invalid M 7 R 7
1191 invalid Z 3
1192 m68k_fetch_dst_ea M R Z
1193 dst:Z = 0
1194 update_flags N0Z1V0C0
1195 m68k_save_dst Z
1196 m68k_prefetch
1197
1156 0100111001110000 reset 1198 0100111001110000 reset
1157 cycles 124
1158 if reset_handler 1199 if reset_handler
1159 pcall reset_handler m68k_reset_handler context 1200 pcall reset_handler m68k_reset_handler context
1160 end 1201 end
1202 cycles 128
1203 m68k_prefetch