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comparison cpu_dsl.py @ 2448:d1eec03dca09

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Fix some issues in new 68K core and add implementations of negx and clr instructions
author Michael Pavone <pavone@retrodev.com>
date Thu, 15 Feb 2024 21:49:17 -0800
parents 461fffc226e0
children edd73a009537
comparison
equal deleted inserted replaced
2447:414eb8c34198 2448:d1eec03dca09
46 elif parts[0] == 'end': 46 elif parts[0] == 'end':
47 raise Exception('end is only allowed inside a switch or if block') 47 raise Exception('end is only allowed inside a switch or if block')
48 else: 48 else:
49 if len(parts) > 1 and parts[1] in assignmentOps: 49 if len(parts) > 1 and parts[1] in assignmentOps:
50 dst = parts[0] 50 dst = parts[0]
51 dst,_,size = dst.partition(':')
51 op = parts[1] 52 op = parts[1]
52 parts = [assignmentOps[op]] + parts[2:] 53 parts = [assignmentOps[op]] + parts[2:]
53 if op == '=': 54 if op == '=':
54 if len(parts) > 2 and parts[2] in binaryOps: 55 if len(parts) > 2 and parts[2] in binaryOps:
55 op = parts[2] 56 op = parts[2]
67 if op == '<<=' or op == '>>=': 68 if op == '<<=' or op == '>>=':
68 parts.insert(1, dst) 69 parts.insert(1, dst)
69 else: 70 else:
70 parts.append(dst) 71 parts.append(dst)
71 parts.append(dst) 72 parts.append(dst)
73 if size:
74 parts.append(size)
72 self.addOp(NormalOp(parts)) 75 self.addOp(NormalOp(parts))
73 return self 76 return self
74 77
75 def processOps(self, prog, fieldVals, output, otype, oplist): 78 def processOps(self, prog, fieldVals, output, otype, oplist):
76 for i in range(0, len(oplist)): 79 for i in range(0, len(oplist)):
343 needsOflow = True 346 needsOflow = True
344 decl = '' 347 decl = ''
345 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust): 348 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust):
346 if len(params) <= 3: 349 if len(params) <= 3:
347 size = prog.paramSize(rawParams[2]) 350 size = prog.paramSize(rawParams[2])
348 if needsCarry and op != 'lsr': 351 if needsCarry and op != '>>':
349 size *= 2 352 size *= 2
350 decl,name = prog.getTemp(size) 353 decl,name = prog.getTemp(size)
351 dst = prog.carryFlowDst = name 354 dst = prog.carryFlowDst = name
352 prog.lastA = a 355 prog.lastA = a
353 prog.lastB = b 356 prog.lastB = b
487 myRes = lastDst 490 myRes = lastDst
488 if calc == 'sign': 491 if calc == 'sign':
489 resultBit = prog.getLastSize() - 1 492 resultBit = prog.getLastSize() - 1
490 elif calc == 'carry': 493 elif calc == 'carry':
491 if prog.lastOp.op in ('asr', 'lsr'): 494 if prog.lastOp.op in ('asr', 'lsr'):
492 resultBit = 0 495 if type(prog.lastB) is int:
496 resultBit = prog.lastB - 1
497 else:
498 #FIXME!!!!!
499 resultBit = 0
493 myRes = prog.lastA 500 myRes = prog.lastA
494 else: 501 else:
495 resultBit = prog.getLastSize() 502 resultBit = prog.getLastSize()
496 if prog.lastOp.op == 'ror': 503 if prog.lastOp.op == 'ror':
497 resultBit -= 1 504 resultBit -= 1