Mercurial > repos > blastem
comparison svp.cpu @ 1614:c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
author | Michael Pavone <pavone@retrodev.com> |
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date | Fri, 21 Sep 2018 09:26:12 -0700 |
parents | 2d9e8a7b8ba2 |
children | 28f80d1b343e |
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1613:2d9e8a7b8ba2 | 1614:c9639139aedf |
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69 | 69 |
70 case 2 | 70 case 2 |
71 #loop decremenet | 71 #loop decremenet |
72 meta modestr - | 72 meta modestr - |
73 mov reg tmp | 73 mov reg tmp |
74 switch rpl | 74 |
75 case 0 | 75 if rpl |
76 sub 1 reg reg | |
77 | |
78 default | |
79 lsl 1 rpl rpl | 76 lsl 1 rpl rpl |
80 sub 1 rpl rpl | 77 sub 1 rpl rpl |
81 local mask 16 | 78 local mask 16 |
82 not rpl mask | 79 not rpl mask |
83 and reg mask reg | 80 and reg mask reg |
84 sub 1 tmp tmp | 81 sub 1 tmp tmp |
85 and rpl tmp tmp | 82 and rpl tmp tmp |
86 or rpl reg reg | 83 or rpl reg reg |
87 | 84 else |
88 end | 85 sub 1 reg reg |
86 end | |
89 | 87 |
90 case 3 | 88 case 3 |
91 #loop increment | 89 #loop increment |
92 meta modestr + | 90 meta modestr + |
93 | 91 |
94 and 7 st rpl | 92 and 7 st rpl |
95 switch rpl | 93 if rpl |
96 case 0 | |
97 sub 1 reg reg | |
98 | |
99 default | |
100 mov reg tmp | 94 mov reg tmp |
101 lsl 1 rpl rpl | 95 lsl 1 rpl rpl |
102 sub 1 rpl rpl | 96 sub 1 rpl rpl |
103 local mask 16 | 97 local mask 16 |
104 not rpl mask | 98 not rpl mask |
105 and reg mask reg | 99 and reg mask reg |
106 add 1 tmp tmp | 100 add 1 tmp tmp |
107 and rpl tmp tmp | 101 and rpl tmp tmp |
108 or rpl reg reg | 102 or rpl reg reg |
109 | 103 else |
110 end | 104 sub 1 reg reg |
111 end | 105 end |
112 | 106 |
113 and 255 idx idx | 107 and 255 idx idx |
114 meta val bank.idx | 108 meta val bank.idx |
115 | 109 |
182 meta flag nflag | 176 meta flag nflag |
183 | 177 |
184 default | 178 default |
185 meta flag 0 | 179 meta flag 0 |
186 end | 180 end |
187 switch fval | 181 |
188 case 0 | 182 if fval |
183 meta istrue flag | |
184 | |
185 else | |
189 lnot flag invert | 186 lnot flag invert |
190 meta istrue invert | 187 meta istrue invert |
191 | 188 |
192 default | |
193 meta istrue flag | |
194 end | 189 end |
195 | 190 |
196 PPP0000000000000 alu_n1 | 191 PPP0000000000000 alu_n1 |
197 invalid P 0 | 192 invalid P 0 |
198 invalid P 2 | 193 invalid P 2 |
280 meta name al | 275 meta name al |
281 svp_alu_op P tmp | 276 svp_alu_op P tmp |
282 | 277 |
283 1001000FCCCC0OOO cond_mod | 278 1001000FCCCC0OOO cond_mod |
284 svp_check_cond F C | 279 svp_check_cond F C |
285 switch istrue | 280 if istrue |
286 case 0 | 281 |
287 | |
288 default | |
289 switch O | 282 switch O |
290 case 2 | 283 case 2 |
291 asr a 1 a | 284 asr a 1 a |
292 update_flags ZN | 285 update_flags ZN |
293 | 286 |
300 update_flags ZN | 293 update_flags ZN |
301 | 294 |
302 case 7 | 295 case 7 |
303 abs a a | 296 abs a a |
304 update_flags N | 297 update_flags N |
298 end | |
305 end | 299 end |
306 | 300 |
307 000000000DDD0SSS ld_int_int | 301 000000000DDD0SSS ld_int_int |
308 dis "ld %s, %s" internal.D internal.S | 302 dis "ld %s, %s" internal.D internal.S |
309 mov internal.S internal.D | 303 mov internal.S internal.D |
506 svp_push val | 500 svp_push val |
507 | 501 |
508 0100100FCCCC0000 call_cond | 502 0100100FCCCC0000 call_cond |
509 svp_check_cond F C | 503 svp_check_cond F C |
510 svp_op_fetch | 504 svp_op_fetch |
511 switch istrue | 505 |
512 case 0 | 506 if istrue |
513 | |
514 default | |
515 svp_push pc | 507 svp_push pc |
516 mov scratch1 pc | 508 mov scratch1 pc |
517 end | 509 end |
518 | 510 |
519 0100110FCCCC0000 bra_cond | 511 0100110FCCCC0000 bra_cond |
520 svp_check_cond F C | 512 svp_check_cond F C |
521 svp_op_fetch | 513 svp_op_fetch |
522 switch istrue | 514 if istrue |
523 case 0 | |
524 | |
525 default | |
526 mov scratch1 pc | 515 mov scratch1 pc |
527 end | 516 end |
528 | 517 |
529 svp_op_fetch | 518 svp_op_fetch |
530 cycles 1 | 519 cycles 1 |