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Clean up symbol visiblity and delete a ltitle bit of dead code
author Michael Pavone <pavone@retrodev.com>
date Mon, 28 Nov 2016 22:45:46 -0800
parents 1a66d5165ea7
children 22e87b739ad6
comparison
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1101:e2d345e351b5 1102:c15896605bf2
37 #define VBLANK_START_H40 (LINE_CHANGE_H40+2) 37 #define VBLANK_START_H40 (LINE_CHANGE_H40+2)
38 #define VBLANK_START_H32 (LINE_CHANGE_H32+2) 38 #define VBLANK_START_H32 (LINE_CHANGE_H32+2)
39 #define FIFO_LATENCY 3 39 #define FIFO_LATENCY 3
40 40
41 int32_t color_map[1 << 12]; 41 int32_t color_map[1 << 12];
42 uint8_t levels[] = {0, 27, 49, 71, 87, 103, 119, 130, 146, 157, 174, 190, 206, 228, 255}; 42 static uint8_t levels[] = {0, 27, 49, 71, 87, 103, 119, 130, 146, 157, 174, 190, 206, 228, 255};
43 43
44 uint8_t debug_base[][3] = { 44 static uint8_t debug_base[][3] = {
45 {127, 127, 127}, //BG 45 {127, 127, 127}, //BG
46 {0, 0, 127}, //A 46 {0, 0, 127}, //A
47 {127, 0, 0}, //Window 47 {127, 0, 0}, //Window
48 {0, 127, 0}, //B 48 {0, 127, 0}, //B
49 {127, 0, 127} //Sprites 49 {127, 0, 127} //Sprites
50 }; 50 };
51 51
52 uint8_t color_map_init_done; 52 static uint8_t color_map_init_done;
53 53
54 void init_vdp_context(vdp_context * context, uint8_t region_pal) 54 void init_vdp_context(vdp_context * context, uint8_t region_pal)
55 { 55 {
56 memset(context, 0, sizeof(*context)); 56 memset(context, 0, sizeof(*context));
57 context->vdpmem = malloc(VRAM_SIZE); 57 context->vdpmem = malloc(VRAM_SIZE);
144 free(context->vdpmem); 144 free(context->vdpmem);
145 free(context->linebuf); 145 free(context->linebuf);
146 free(context); 146 free(context);
147 } 147 }
148 148
149 int is_refresh(vdp_context * context, uint32_t slot) 149 static int is_refresh(vdp_context * context, uint32_t slot)
150 { 150 {
151 if (context->regs[REG_MODE_4] & BIT_H40) { 151 if (context->regs[REG_MODE_4] & BIT_H40) {
152 return slot == 250 || slot == 26 || slot == 59 || slot == 90 || slot == 122 || slot == 154; 152 return slot == 250 || slot == 26 || slot == 59 || slot == 90 || slot == 122 || slot == 154;
153 } else { 153 } else {
154 //TODO: Figure out which slots are refresh when display is off in 32-cell mode 154 //TODO: Figure out which slots are refresh when display is off in 32-cell mode
157 //The numbers below are the refresh slots during active display 157 //The numbers below are the refresh slots during active display
158 //return (slot == 29 || slot == 61 || slot == 93 || slot == 125); 158 //return (slot == 29 || slot == 61 || slot == 93 || slot == 125);
159 } 159 }
160 } 160 }
161 161
162 void render_sprite_cells(vdp_context * context) 162 static void render_sprite_cells(vdp_context * context)
163 { 163 {
164 if (context->cur_slot >= context->sprite_draws) { 164 if (context->cur_slot >= context->sprite_draws) {
165 sprite_draw * d = context->sprite_draw_list + context->cur_slot; 165 sprite_draw * d = context->sprite_draw_list + context->cur_slot;
166 166
167 uint16_t dir; 167 uint16_t dir;
249 // D = VRAM8 write alias 249 // D = VRAM8 write alias
250 // F = VRAM8 write alais 250 // F = VRAM8 write alais
251 251
252 #define DMA_START 0x20 252 #define DMA_START 0x20
253 253
254 const char * cd_name(uint8_t cd) 254 static const char * cd_name(uint8_t cd)
255 { 255 {
256 switch (cd & 0xF) 256 switch (cd & 0xF)
257 { 257 {
258 case VRAM_READ: 258 case VRAM_READ:
259 return "VRAM read"; 259 return "VRAM read";
336 (context->flags2 & FLAG2_HINT_PENDING) ? "true" : "false", vdp_control_port_read(context)); 336 (context->flags2 & FLAG2_HINT_PENDING) ? "true" : "false", vdp_control_port_read(context));
337 337
338 //TODO: Window Group, DMA Group 338 //TODO: Window Group, DMA Group
339 } 339 }
340 340
341 void scan_sprite_table(uint32_t line, vdp_context * context) 341 static void scan_sprite_table(uint32_t line, vdp_context * context)
342 { 342 {
343 if (context->sprite_index && context->slot_counter) { 343 if (context->sprite_index && context->slot_counter) {
344 line += 1; 344 line += 1;
345 line &= 0xFF; 345 line &= 0xFF;
346 uint16_t ymask, ymin; 346 uint16_t ymask, ymin;
404 context->sprite_index = context->sat_cache[address+3] & 0x7F; 404 context->sprite_index = context->sat_cache[address+3] & 0x7F;
405 } 405 }
406 } 406 }
407 } 407 }
408 408
409 void read_sprite_x(uint32_t line, vdp_context * context) 409 static void read_sprite_x(uint32_t line, vdp_context * context)
410 { 410 {
411 if (context->cur_slot >= context->slot_counter) { 411 if (context->cur_slot >= context->slot_counter) {
412 if (context->sprite_draws) { 412 if (context->sprite_draws) {
413 line += 1; 413 line += 1;
414 line &= 0xFF; 414 line &= 0xFF;
481 context->flags |= FLAG_DOT_OFLOW; 481 context->flags |= FLAG_DOT_OFLOW;
482 } 482 }
483 } 483 }
484 } 484 }
485 485
486 void write_cram(vdp_context * context, uint16_t address, uint16_t value) 486 static void write_cram(vdp_context * context, uint16_t address, uint16_t value)
487 { 487 {
488 uint16_t addr = (address/2) & (CRAM_SIZE-1); 488 uint16_t addr = (address/2) & (CRAM_SIZE-1);
489 context->cram[addr] = value; 489 context->cram[addr] = value;
490 context->colors[addr] = color_map[value & 0xEEE]; 490 context->colors[addr] = color_map[value & 0xEEE];
491 context->colors[addr + CRAM_SIZE] = color_map[(value & 0xEEE) | FBUF_SHADOW]; 491 context->colors[addr + CRAM_SIZE] = color_map[(value & 0xEEE) | FBUF_SHADOW];
494 494
495 #define CRAM_BITS 0xEEE 495 #define CRAM_BITS 0xEEE
496 #define VSRAM_BITS 0x7FF 496 #define VSRAM_BITS 0x7FF
497 #define VSRAM_DIRTY_BITS 0xF800 497 #define VSRAM_DIRTY_BITS 0xF800
498 498
499 void vdp_advance_dma(vdp_context * context) 499 static void vdp_advance_dma(vdp_context * context)
500 { 500 {
501 context->regs[REG_DMASRC_L] += 1; 501 context->regs[REG_DMASRC_L] += 1;
502 if (!context->regs[REG_DMASRC_L]) { 502 if (!context->regs[REG_DMASRC_L]) {
503 context->regs[REG_DMASRC_M] += 1; 503 context->regs[REG_DMASRC_M] += 1;
504 } 504 }
523 } 523 }
524 } 524 }
525 context->vdpmem[address] = value; 525 context->vdpmem[address] = value;
526 } 526 }
527 527
528 void external_slot(vdp_context * context) 528 static void external_slot(vdp_context * context)
529 { 529 {
530 if ((context->flags & FLAG_DMA_RUN) && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80 && context->fifo_read < 0) { 530 if ((context->flags & FLAG_DMA_RUN) && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80 && context->fifo_read < 0) {
531 context->fifo_read = (context->fifo_write-1) & (FIFO_SIZE-1); 531 context->fifo_read = (context->fifo_write-1) & (FIFO_SIZE-1);
532 fifo_entry * cur = context->fifo + context->fifo_read; 532 fifo_entry * cur = context->fifo + context->fifo_read;
533 cur->cycle = context->cycles; 533 cur->cycle = context->cycles;
627 } 627 }
628 } 628 }
629 } 629 }
630 } 630 }
631 631
632 void run_dma_src(vdp_context * context, int32_t slot) 632 static void run_dma_src(vdp_context * context, int32_t slot)
633 { 633 {
634 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode 634 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode
635 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations 635 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations
636 if (context->fifo_write == context->fifo_read) { 636 if (context->fifo_write == context->fifo_read) {
637 return; 637 return;
657 } 657 }
658 658
659 #define WINDOW_RIGHT 0x80 659 #define WINDOW_RIGHT 0x80
660 #define WINDOW_DOWN 0x80 660 #define WINDOW_DOWN 0x80
661 661
662 void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context) 662 static void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context)
663 { 663 {
664 uint16_t window_line_shift, v_offset_mask, vscroll_shift; 664 uint16_t window_line_shift, v_offset_mask, vscroll_shift;
665 if (context->double_res) { 665 if (context->double_res) {
666 line *= 2; 666 line *= 2;
667 if (context->flags2 & FLAG2_EVEN_FIELD) { 667 if (context->flags2 & FLAG2_EVEN_FIELD) {
802 context->col_1 = col_val; 802 context->col_1 = col_val;
803 } 803 }
804 } 804 }
805 } 805 }
806 806
807 void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context) 807 static void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context)
808 { 808 {
809 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context); 809 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context);
810 } 810 }
811 811
812 void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context) 812 static void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context)
813 { 813 {
814 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context); 814 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context);
815 } 815 }
816 816
817 void render_map(uint16_t col, uint8_t * tmp_buf, uint8_t offset, vdp_context * context) 817 static void render_map(uint16_t col, uint8_t * tmp_buf, uint8_t offset, vdp_context * context)
818 { 818 {
819 uint16_t address; 819 uint16_t address;
820 uint16_t vflip_base; 820 uint16_t vflip_base;
821 if (context->double_res) { 821 if (context->double_res) {
822 address = ((col & 0x3FF) << 6); 822 address = ((col & 0x3FF) << 6);
848 offset += dir; 848 offset += dir;
849 offset &= SCROLL_BUFFER_MASK; 849 offset &= SCROLL_BUFFER_MASK;
850 } 850 }
851 } 851 }
852 852
853 void render_map_1(vdp_context * context) 853 static void render_map_1(vdp_context * context)
854 { 854 {
855 render_map(context->col_1, context->tmp_buf_a, context->buf_a_off, context); 855 render_map(context->col_1, context->tmp_buf_a, context->buf_a_off, context);
856 } 856 }
857 857
858 void render_map_2(vdp_context * context) 858 static void render_map_2(vdp_context * context)
859 { 859 {
860 render_map(context->col_2, context->tmp_buf_a, context->buf_a_off+8, context); 860 render_map(context->col_2, context->tmp_buf_a, context->buf_a_off+8, context);
861 } 861 }
862 862
863 void render_map_3(vdp_context * context) 863 static void render_map_3(vdp_context * context)
864 { 864 {
865 render_map(context->col_1, context->tmp_buf_b, context->buf_b_off, context); 865 render_map(context->col_1, context->tmp_buf_b, context->buf_b_off, context);
866 } 866 }
867 867
868 void render_map_output(uint32_t line, int32_t col, vdp_context * context) 868 static void render_map_output(uint32_t line, int32_t col, vdp_context * context)
869 { 869 {
870 if (line >= 240) { 870 if (line >= 240) {
871 return; 871 return;
872 } 872 }
873 render_map(context->col_2, context->tmp_buf_b, context->buf_b_off+8, context); 873 render_map(context->col_2, context->tmp_buf_b, context->buf_b_off+8, context);
1013 } 1013 }
1014 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK; 1014 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
1015 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK; 1015 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
1016 } 1016 }
1017 1017
1018 uint32_t const h40_hsync_cycles[] = {19, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 19}; 1018 static uint32_t const h40_hsync_cycles[] = {19, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 19};
1019 1019
1020 void vdp_advance_line(vdp_context *context) 1020 static void vdp_advance_line(vdp_context *context)
1021 { 1021 {
1022 context->vcounter++; 1022 context->vcounter++;
1023 context->vcounter &= 0x1FF; 1023 context->vcounter &= 0x1FF;
1024 if (context->flags2 & FLAG2_REGION_PAL) { 1024 if (context->flags2 & FLAG2_REGION_PAL) {
1025 if (context->latched_mode & BIT_PAL) { 1025 if (context->latched_mode & BIT_PAL) {
1149 }\ 1149 }\
1150 context->cycles += slot_cycles;\ 1150 context->cycles += slot_cycles;\
1151 CHECK_ONLY 1151 CHECK_ONLY
1152 1152
1153 1153
1154 void vdp_h40(vdp_context * context, uint32_t target_cycles) 1154 static void vdp_h40(vdp_context * context, uint32_t target_cycles)
1155 { 1155 {
1156 uint16_t address; 1156 uint16_t address;
1157 uint32_t mask; 1157 uint32_t mask;
1158 uint32_t const slot_cycles = MCLKS_SLOT_H40; 1158 uint32_t const slot_cycles = MCLKS_SLOT_H40;
1159 switch(context->hslot) 1159 switch(context->hslot)
1309 context->cycles += slot_cycles; 1309 context->cycles += slot_cycles;
1310 return; 1310 return;
1311 } 1311 }
1312 } 1312 }
1313 1313
1314 void vdp_h32(vdp_context * context, uint32_t target_cycles) 1314 static void vdp_h32(vdp_context * context, uint32_t target_cycles)
1315 { 1315 {
1316 uint16_t address; 1316 uint16_t address;
1317 uint32_t mask; 1317 uint32_t mask;
1318 uint32_t const slot_cycles = MCLKS_SLOT_H32; 1318 uint32_t const slot_cycles = MCLKS_SLOT_H32;
1319 switch(context->hslot) 1319 switch(context->hslot)
1460 void latch_mode(vdp_context * context) 1460 void latch_mode(vdp_context * context)
1461 { 1461 {
1462 context->latched_mode = context->regs[REG_MODE_2] & BIT_PAL; 1462 context->latched_mode = context->regs[REG_MODE_2] & BIT_PAL;
1463 } 1463 }
1464 1464
1465 void check_render_bg(vdp_context * context, int32_t line, uint32_t slot) 1465 static void check_render_bg(vdp_context * context, int32_t line, uint32_t slot)
1466 { 1466 {
1467 int starti = -1; 1467 int starti = -1;
1468 if (context->regs[REG_MODE_4] & BIT_H40) { 1468 if (context->regs[REG_MODE_4] & BIT_H40) {
1469 if (slot >= 12 && slot < 172) { 1469 if (slot >= 12 && slot < 172) {
1470 starti = (slot-12)*2; 1470 starti = (slot-12)*2;
1828 idx = (idx+1) & (FIFO_SIZE-1); 1828 idx = (idx+1) & (FIFO_SIZE-1);
1829 } while(idx != context->fifo_write); 1829 } while(idx != context->fifo_write);
1830 } 1830 }
1831 } 1831 }
1832 1832
1833 uint32_t vdp_cycles_hslot_wrap_h40(vdp_context * context) 1833 static uint32_t vdp_cycles_hslot_wrap_h40(vdp_context * context)
1834 { 1834 {
1835 if (context->hslot < 183) { 1835 if (context->hslot < 183) {
1836 return MCLKS_LINE - context->hslot * MCLKS_SLOT_H40; 1836 return MCLKS_LINE - context->hslot * MCLKS_SLOT_H40;
1837 } else if (context->hslot < HSYNC_END_H40) { 1837 } else if (context->hslot < HSYNC_END_H40) {
1838 uint32_t before_hsync = context->hslot < HSYNC_SLOT_H40 ? (HSYNC_SLOT_H40 - context->hslot) * MCLKS_SLOT_H40 : 0; 1838 uint32_t before_hsync = context->hslot < HSYNC_SLOT_H40 ? (HSYNC_SLOT_H40 - context->hslot) * MCLKS_SLOT_H40 : 0;
1846 } else { 1846 } else {
1847 return (256-context->hslot) * MCLKS_SLOT_H40; 1847 return (256-context->hslot) * MCLKS_SLOT_H40;
1848 } 1848 }
1849 } 1849 }
1850 1850
1851 uint32_t vdp_cycles_next_line(vdp_context * context) 1851 static uint32_t vdp_cycles_next_line(vdp_context * context)
1852 { 1852 {
1853 if (context->regs[REG_MODE_4] & BIT_H40) { 1853 if (context->regs[REG_MODE_4] & BIT_H40) {
1854 if (context->hslot < LINE_CHANGE_H40) { 1854 if (context->hslot < LINE_CHANGE_H40) {
1855 return (LINE_CHANGE_H40 - context->hslot) * MCLKS_SLOT_H40; 1855 return (LINE_CHANGE_H40 - context->hslot) * MCLKS_SLOT_H40;
1856 } else { 1856 } else {
1865 return (256-context->hslot + LINE_CHANGE_H32) * MCLKS_SLOT_H32; 1865 return (256-context->hslot + LINE_CHANGE_H32) * MCLKS_SLOT_H32;
1866 } 1866 }
1867 } 1867 }
1868 } 1868 }
1869 1869
1870 uint32_t vdp_cycles_to_line(vdp_context * context, uint32_t target) 1870 static uint32_t vdp_cycles_to_line(vdp_context * context, uint32_t target)
1871 { 1871 {
1872 uint32_t jump_start, jump_dst; 1872 uint32_t jump_start, jump_dst;
1873 if (context->flags2 & FLAG2_REGION_PAL) { 1873 if (context->flags2 & FLAG2_REGION_PAL) {
1874 if (context->latched_mode & BIT_PAL) { 1874 if (context->latched_mode & BIT_PAL) {
1875 jump_start = 0x10B; 1875 jump_start = 0x10B;
1907 } 1907 }
1908 } 1908 }
1909 return MCLKS_LINE * (lines - 1) + vdp_cycles_next_line(context); 1909 return MCLKS_LINE * (lines - 1) + vdp_cycles_next_line(context);
1910 } 1910 }
1911 1911
1912 uint32_t vdp_frame_end_line(vdp_context * context) 1912 static uint32_t vdp_frame_end_line(vdp_context * context)
1913 { 1913 {
1914 uint32_t frame_end; 1914 uint32_t frame_end;
1915 if (context->flags2 & FLAG2_REGION_PAL) { 1915 if (context->flags2 & FLAG2_REGION_PAL) {
1916 if (context->latched_mode & BIT_PAL) { 1916 if (context->latched_mode & BIT_PAL) {
1917 frame_end = PAL_INACTIVE_START + 8; 1917 frame_end = PAL_INACTIVE_START + 8;