Mercurial > repos > blastem
comparison vdp.h @ 487:c08a4efeee7f opengl
Update opengl branch from default. Fix build breakage unrelated to merge
author | Mike Pavone <pavone@retrodev.com> |
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date | Sat, 26 Oct 2013 22:38:47 -0700 |
parents | 0737953132ad |
children | 8ac0eb05642c |
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449:7696d824489d | 487:c08a4efeee7f |
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1 /* | |
2 Copyright 2013 Michael Pavone | |
3 This file is part of BlastEm. | |
4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. | |
5 */ | |
1 #ifndef VDP_H_ | 6 #ifndef VDP_H_ |
2 #define VDP_H_ | 7 #define VDP_H_ |
3 | 8 |
4 #include <stdint.h> | 9 #include <stdint.h> |
5 #include <stdio.h> | 10 #include <stdio.h> |
17 #define MAX_SPRITES_FRAME 80 | 22 #define MAX_SPRITES_FRAME 80 |
18 #define MAX_SPRITES_FRAME_H32 64 | 23 #define MAX_SPRITES_FRAME_H32 64 |
19 | 24 |
20 #define FBUF_SHADOW 0x0001 | 25 #define FBUF_SHADOW 0x0001 |
21 #define FBUF_HILIGHT 0x0010 | 26 #define FBUF_HILIGHT 0x0010 |
22 #define FBUF_BIT_PRIORITY 0x1000 | 27 #define DBG_SHADOW 0x10 |
23 #define FBUF_SRC_MASK 0xE000 | 28 #define DBG_HILIGHT 0x20 |
24 #define FBUF_SRC_A 0x0000 | 29 #define DBG_PRIORITY 0x8 |
25 #define FBUF_SRC_W 0x2000 | 30 #define DBG_SRC_MASK 0x7 |
26 #define FBUF_SRC_B 0x4000 | 31 #define DBG_SRC_A 0x1 |
27 #define FBUF_SRC_S 0x6000 | 32 #define DBG_SRC_W 0x2 |
28 #define FBUF_SRC_BG 0x8000 | 33 #define DBG_SRC_B 0x3 |
34 #define DBG_SRC_S 0x4 | |
35 #define DBG_SRC_BG 0x0 | |
29 | 36 |
30 #define MCLKS_LINE 3420 | 37 #define MCLKS_LINE 3420 |
31 | 38 |
32 #define FLAG_DOT_OFLOW 0x01 | 39 #define FLAG_DOT_OFLOW 0x01 |
33 #define FLAG_CAN_MASK 0x02 | 40 #define FLAG_CAN_MASK 0x02 |
38 #define FLAG_DMA_RUN 0x40 | 45 #define FLAG_DMA_RUN 0x40 |
39 #define FLAG_DMA_PROG 0x80 | 46 #define FLAG_DMA_PROG 0x80 |
40 | 47 |
41 #define FLAG2_VINT_PENDING 0x01 | 48 #define FLAG2_VINT_PENDING 0x01 |
42 #define FLAG2_HINT_PENDING 0x02 | 49 #define FLAG2_HINT_PENDING 0x02 |
50 #define FLAG2_READ_PENDING 0x04 | |
43 | 51 |
44 #define DISPLAY_ENABLE 0x40 | 52 #define DISPLAY_ENABLE 0x40 |
45 | 53 |
46 enum { | 54 enum { |
47 REG_MODE_1=0, | 55 REG_MODE_1=0, |
100 uint8_t size; | 108 uint8_t size; |
101 uint8_t index; | 109 uint8_t index; |
102 int16_t y; | 110 int16_t y; |
103 } sprite_info; | 111 } sprite_info; |
104 | 112 |
113 #define FIFO_SIZE 4 | |
114 | |
105 typedef struct { | 115 typedef struct { |
106 uint32_t cycle; | 116 uint32_t cycle; |
107 uint16_t address; | 117 uint16_t address; |
108 uint16_t value; | 118 uint16_t value; |
109 uint8_t cd; | 119 uint8_t cd; |
110 uint8_t partial; | 120 uint8_t partial; |
111 } fifo_entry; | 121 } fifo_entry; |
112 | 122 |
113 typedef struct { | 123 typedef struct { |
114 fifo_entry *fifo_cur; | 124 fifo_entry fifo[FIFO_SIZE]; |
115 fifo_entry *fifo_end; | 125 int32_t fifo_write; |
126 int32_t fifo_read; | |
116 uint16_t address; | 127 uint16_t address; |
117 uint8_t cd; | 128 uint8_t cd; |
118 uint8_t flags; | 129 uint8_t flags; |
119 uint8_t regs[VDP_REGS]; | 130 uint8_t regs[VDP_REGS]; |
120 //cycle count in MCLKs | 131 //cycle count in MCLKs |
126 void *framebuf; | 137 void *framebuf; |
127 void *oddbuf; | 138 void *oddbuf; |
128 void *evenbuf; | 139 void *evenbuf; |
129 uint16_t cram[CRAM_SIZE]; | 140 uint16_t cram[CRAM_SIZE]; |
130 uint32_t colors[CRAM_SIZE*3]; | 141 uint32_t colors[CRAM_SIZE*3]; |
142 uint32_t debugcolors[1 << (3 + 1 + 1 + 1)];//3 bits for source, 1 bit for priority, 1 bit for shadow, 1 bit for hilight | |
131 uint16_t vsram[VSRAM_SIZE]; | 143 uint16_t vsram[VSRAM_SIZE]; |
132 uint8_t latched_mode; | 144 uint8_t latched_mode; |
133 uint16_t hscroll_a; | 145 uint16_t hscroll_a; |
134 uint16_t hscroll_b; | 146 uint16_t hscroll_b; |
135 uint8_t sprite_index; | 147 uint8_t sprite_index; |
138 int8_t cur_slot; | 150 int8_t cur_slot; |
139 sprite_draw sprite_draw_list[MAX_DRAWS]; | 151 sprite_draw sprite_draw_list[MAX_DRAWS]; |
140 sprite_info sprite_info_list[MAX_SPRITES_LINE]; | 152 sprite_info sprite_info_list[MAX_SPRITES_LINE]; |
141 uint16_t col_1; | 153 uint16_t col_1; |
142 uint16_t col_2; | 154 uint16_t col_2; |
143 uint16_t dma_val; | 155 uint16_t hv_latch; |
144 uint8_t v_offset; | 156 uint8_t v_offset; |
145 uint8_t dma_cd; | 157 uint8_t dma_cd; |
146 uint8_t hint_counter; | 158 uint8_t hint_counter; |
147 uint8_t flags2; | 159 uint8_t flags2; |
148 uint8_t double_res; | 160 uint8_t double_res; |
149 uint8_t b32; | 161 uint8_t b32; |
162 uint8_t buf_a_off; | |
163 uint8_t buf_b_off; | |
164 uint8_t debug; | |
150 uint8_t *tmp_buf_a; | 165 uint8_t *tmp_buf_a; |
151 uint8_t *tmp_buf_b; | 166 uint8_t *tmp_buf_b; |
152 } vdp_context; | 167 } vdp_context; |
153 | 168 |
154 void init_vdp_context(vdp_context * context); | 169 void init_vdp_context(vdp_context * context); |
156 //runs from current cycle count to VBLANK for the current mode, returns ending cycle count | 171 //runs from current cycle count to VBLANK for the current mode, returns ending cycle count |
157 uint32_t vdp_run_to_vblank(vdp_context * context); | 172 uint32_t vdp_run_to_vblank(vdp_context * context); |
158 //runs until the target cycle is reached or the current DMA operation has completed, whicever comes first | 173 //runs until the target cycle is reached or the current DMA operation has completed, whicever comes first |
159 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles); | 174 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles); |
160 uint8_t vdp_load_gst(vdp_context * context, FILE * state_file); | 175 uint8_t vdp_load_gst(vdp_context * context, FILE * state_file); |
161 void vdp_save_state(vdp_context * context, FILE * outfile); | 176 uint8_t vdp_save_gst(vdp_context * context, FILE * outfile); |
162 int vdp_control_port_write(vdp_context * context, uint16_t value); | 177 int vdp_control_port_write(vdp_context * context, uint16_t value); |
163 int vdp_data_port_write(vdp_context * context, uint16_t value); | 178 int vdp_data_port_write(vdp_context * context, uint16_t value); |
179 void vdp_test_port_write(vdp_context * context, uint16_t value); | |
164 uint16_t vdp_control_port_read(vdp_context * context); | 180 uint16_t vdp_control_port_read(vdp_context * context); |
165 uint16_t vdp_data_port_read(vdp_context * context); | 181 uint16_t vdp_data_port_read(vdp_context * context); |
166 uint16_t vdp_hv_counter_read(vdp_context * context); | 182 uint16_t vdp_hv_counter_read(vdp_context * context); |
183 uint16_t vdp_test_port_read(vdp_context * context); | |
167 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction); | 184 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction); |
168 uint32_t vdp_next_hint(vdp_context * context); | 185 uint32_t vdp_next_hint(vdp_context * context); |
169 uint32_t vdp_next_vint(vdp_context * context); | 186 uint32_t vdp_next_vint(vdp_context * context); |
170 uint32_t vdp_next_vint_z80(vdp_context * context); | 187 uint32_t vdp_next_vint_z80(vdp_context * context); |
171 void vdp_int_ack(vdp_context * context, uint16_t int_num); | 188 void vdp_int_ack(vdp_context * context, uint16_t int_num); |
172 void vdp_print_sprite_table(vdp_context * context); | 189 void vdp_print_sprite_table(vdp_context * context); |
173 void vdp_print_reg_explain(vdp_context * context); | 190 void vdp_print_reg_explain(vdp_context * context); |
191 void latch_mode(vdp_context * context); | |
192 | |
193 extern int32_t color_map[1 << 12]; | |
174 | 194 |
175 #endif //VDP_H_ | 195 #endif //VDP_H_ |