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comparison vdp.h @ 1318:bfdd450e7dea

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Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support
author Michael Pavone <pavone@retrodev.com>
date Sun, 16 Apr 2017 16:40:04 -0700
parents 3772bb926be5
children b1423d432c0e
comparison
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1317:32e95d6733a6 1318:bfdd450e7dea
99 #define BIT_MODE_4 BIT_PAL_SEL 99 #define BIT_MODE_4 BIT_PAL_SEL
100 #define BIT_HVC_LATCH 0x02 100 #define BIT_HVC_LATCH 0x02
101 #define BIT_DISP_DIS 0x01 101 #define BIT_DISP_DIS 0x01
102 102
103 //Mode reg 2 103 //Mode reg 2
104 #define BIT_128K_VRAM 0x80
104 #define BIT_DISP_EN 0x40 105 #define BIT_DISP_EN 0x40
105 #define BIT_VINT_EN 0x20 106 #define BIT_VINT_EN 0x20
106 #define BIT_DMA_ENABLE 0x10 107 #define BIT_DMA_ENABLE 0x10
107 #define BIT_PAL 0x08 108 #define BIT_PAL 0x08
108 #define BIT_MODE_5 0x04 109 #define BIT_MODE_5 0x04
133 134
134 #define FIFO_SIZE 4 135 #define FIFO_SIZE 4
135 136
136 typedef struct { 137 typedef struct {
137 uint32_t cycle; 138 uint32_t cycle;
138 uint16_t address; 139 uint32_t address;
139 uint16_t value; 140 uint16_t value;
140 uint8_t cd; 141 uint8_t cd;
141 uint8_t partial; 142 uint8_t partial;
142 } fifo_entry; 143 } fifo_entry;
143 144
144 typedef struct { 145 typedef struct {
145 fifo_entry fifo[FIFO_SIZE]; 146 fifo_entry fifo[FIFO_SIZE];
146 int32_t fifo_write; 147 int32_t fifo_write;
147 int32_t fifo_read; 148 int32_t fifo_read;
148 uint16_t address; 149 uint32_t address;
149 uint8_t cd; 150 uint8_t cd;
150 uint8_t flags; 151 uint8_t flags;
151 uint8_t regs[VDP_REGS]; 152 uint8_t regs[VDP_REGS];
152 //cycle count in MCLKs 153 //cycle count in MCLKs
153 uint32_t cycles; 154 uint32_t cycles;
185 uint8_t sat_cache[SAT_CACHE_SIZE]; 186 uint8_t sat_cache[SAT_CACHE_SIZE];
186 uint16_t col_1; 187 uint16_t col_1;
187 uint16_t col_2; 188 uint16_t col_2;
188 uint16_t hv_latch; 189 uint16_t hv_latch;
189 uint16_t prefetch; 190 uint16_t prefetch;
191 uint16_t test_port;
190 uint8_t fetch_tmp[2]; 192 uint8_t fetch_tmp[2];
191 uint8_t v_offset; 193 uint8_t v_offset;
192 uint8_t dma_cd; 194 uint8_t dma_cd;
193 uint8_t hint_counter; 195 uint8_t hint_counter;
194 uint8_t flags2; 196 uint8_t flags2;
231 void vdp_print_sprite_table(vdp_context * context); 233 void vdp_print_sprite_table(vdp_context * context);
232 void vdp_print_reg_explain(vdp_context * context); 234 void vdp_print_reg_explain(vdp_context * context);
233 void latch_mode(vdp_context * context); 235 void latch_mode(vdp_context * context);
234 uint32_t vdp_cycles_to_frame_end(vdp_context * context); 236 uint32_t vdp_cycles_to_frame_end(vdp_context * context);
235 void write_cram(vdp_context * context, uint16_t address, uint16_t value); 237 void write_cram(vdp_context * context, uint16_t address, uint16_t value);
236 void write_vram_byte(vdp_context *context, uint16_t address, uint8_t value); 238 void write_vram_byte(vdp_context *context, uint32_t address, uint8_t value);
237 239
238 #endif //VDP_H_ 240 #endif //VDP_H_