Mercurial > repos > blastem
comparison segacd.c @ 2138:b6338e18787e
Fix some dynarec code invalidation issues
author | Michael Pavone <pavone@retrodev.com> |
---|---|
date | Sat, 19 Mar 2022 15:50:45 -0700 |
parents | 3ef9456b76cf |
children | 10e4439d8f13 |
comparison
equal
deleted
inserted
replaced
2137:3ef9456b76cf | 2138:b6338e18787e |
---|---|
155 static void *word_ram_2M_write8(uint32_t address, void *vcontext, uint8_t value) | 155 static void *word_ram_2M_write8(uint32_t address, void *vcontext, uint8_t value) |
156 { | 156 { |
157 m68k_context *m68k = vcontext; | 157 m68k_context *m68k = vcontext; |
158 segacd_context *cd = m68k->system; | 158 segacd_context *cd = m68k->system; |
159 if (!(cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE)) { | 159 if (!(cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE)) { |
160 //TODO: Confirm this first write goes through (seemed like it in initial testing) | |
160 if (address & 1) { | 161 if (address & 1) { |
161 address >>= 1; | 162 address >>= 1; |
162 cd->word_ram[address] &= 0xFF00; | 163 cd->word_ram[address] &= 0xFF00; |
163 cd->word_ram[address] |= value; | 164 cd->word_ram[address] |= value; |
164 } else { | 165 } else { |
165 address >>= 1; | 166 address >>= 1; |
166 cd->word_ram[address] &= 0x00FF; | 167 cd->word_ram[address] &= 0x00FF; |
167 cd->word_ram[address] |= value << 8; | 168 cd->word_ram[address] |= value << 8; |
168 } | 169 } |
170 m68k_invalidate_code_range(cd->genesis->m68k, cd->base + 0x200000 + (address & ~1), cd->base + 0x200000 + (address & ~1) + 1); | |
169 cd->sub_paused_wordram = 1; | 171 cd->sub_paused_wordram = 1; |
170 m68k->sync_cycle = m68k->target_cycle = m68k->current_cycle; | 172 m68k->sync_cycle = m68k->target_cycle = m68k->current_cycle; |
171 m68k->should_return = 1; | 173 m68k->should_return = 1; |
172 } else { | 174 } else { |
173 value &= 0xF; | 175 value &= 0xF; |
205 return word_ram_2M_write8(address + 1, vcontext, value); | 207 return word_ram_2M_write8(address + 1, vcontext, value); |
206 } | 208 } |
207 | 209 |
208 static uint16_t word_ram_1M_read16(uint32_t address, void *vcontext) | 210 static uint16_t word_ram_1M_read16(uint32_t address, void *vcontext) |
209 { | 211 { |
212 //TODO: check behavior for these on hardware | |
210 return 0; | 213 return 0; |
211 } | 214 } |
212 | 215 |
213 static uint8_t word_ram_1M_read8(uint32_t address, void *vcontext) | 216 static uint8_t word_ram_1M_read8(uint32_t address, void *vcontext) |
214 { | 217 { |
298 cd->word_ram[offset] |= value; | 301 cd->word_ram[offset] |= value; |
299 } else { | 302 } else { |
300 cd->word_ram[address + cd->bank_toggle] &= 0xFF; | 303 cd->word_ram[address + cd->bank_toggle] &= 0xFF; |
301 cd->word_ram[address + cd->bank_toggle] |= value << 8; | 304 cd->word_ram[address + cd->bank_toggle] |= value << 8; |
302 } | 305 } |
303 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + (address & ~1), cd->base + 0x200000 + address + 1); | 306 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + (address & ~1), cd->base + 0x200000 + (address & ~1) + 1); |
304 } | 307 } |
305 return vcontext; | 308 return vcontext; |
306 } | 309 } |
307 | 310 |
308 static uint32_t cell_image_translate_address(uint32_t address) | 311 static uint32_t cell_image_translate_address(uint32_t address) |
360 genesis_context *gen = m68k->system; | 363 genesis_context *gen = m68k->system; |
361 segacd_context *cd = gen->expansion; | 364 segacd_context *cd = gen->expansion; |
362 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) { | 365 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) { |
363 address = cell_image_translate_address(address); | 366 address = cell_image_translate_address(address); |
364 cd->word_ram[address + cd->bank_toggle] = value; | 367 cd->word_ram[address + cd->bank_toggle] = value; |
368 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + address, cd->base + 0x200000 + address + 1); | |
365 } | 369 } |
366 return vcontext; | 370 return vcontext; |
367 } | 371 } |
368 | 372 |
369 static void *cell_image_write8(uint32_t address, void *vcontext, uint8_t value) | 373 static void *cell_image_write8(uint32_t address, void *vcontext, uint8_t value) |
379 cd->word_ram[address + cd->bank_toggle] |= value; | 383 cd->word_ram[address + cd->bank_toggle] |= value; |
380 } else { | 384 } else { |
381 cd->word_ram[address + cd->bank_toggle] &= 0x00FF; | 385 cd->word_ram[address + cd->bank_toggle] &= 0x00FF; |
382 cd->word_ram[address + cd->bank_toggle] |= value << 8; | 386 cd->word_ram[address + cd->bank_toggle] |= value << 8; |
383 } | 387 } |
388 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + address, cd->base + 0x200000 + address + 1); | |
384 } | 389 } |
385 return vcontext; | 390 return vcontext; |
386 } | 391 } |
387 | 392 |
388 static void cdd_run(segacd_context *cd, uint32_t cycle) | 393 static void cdd_run(segacd_context *cd, uint32_t cycle) |