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comparison segacd.c @ 2344:ae073c2167e2

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Fix timing of sub CPU level 5 interrupt when main CPU is reading CDC data
author Michael Pavone <pavone@retrodev.com>
date Fri, 06 Oct 2023 00:20:18 -0700
parents c05b7c5e6f11
children f8b5142c06aa
comparison
equal deleted inserted replaced
2343:49bd818ec9d8 2344:ae073c2167e2
1268 case GA_CDC_HOST_DATA: { 1268 case GA_CDC_HOST_DATA: {
1269 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7; 1269 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
1270 if (dst == DST_MAIN_CPU) { 1270 if (dst == DST_MAIN_CPU) {
1271 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) { 1271 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) {
1272 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR; 1272 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR;
1273 lc8951_resume_transfer(&cd->cdc, scd_cycle); 1273 //Using the sub CPU's cycle count here is a bit of a hack
1274 //needed to ensure the interrupt does not get triggered prematurely
1275 //because the sub CPU execution granularity is too high
1276 lc8951_resume_transfer(&cd->cdc, cd->m68k->current_cycle);
1274 } else { 1277 } else {
1275 printf("Read of CDC host data with DSR clear at %u\n", scd_cycle); 1278 printf("Read of CDC host data with DSR clear at %u\n", scd_cycle);
1276 } 1279 }
1277 calculate_target_cycle(cd->m68k); 1280 calculate_target_cycle(cd->m68k);
1278 } 1281 }