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comparison z80_to_x86.c @ 1055:ac4615d16226

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Implement undocumented flag bits for shift instructions
author Michael Pavone <pavone@retrodev.com>
date Fri, 29 Jul 2016 22:06:45 -0700
parents ca38a29d2d76
children 47c748455365
comparison
equal deleted inserted replaced
1054:ca38a29d2d76 1055:ac4615d16226
1671 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B); 1671 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
1672 } 1672 }
1673 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); 1673 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1674 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); 1674 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
1675 if (dst_op.mode == MODE_REG_DIRECT) { 1675 if (dst_op.mode == MODE_REG_DIRECT) {
1676 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1676 cmp_ir(code, 0, dst_op.base, SZ_B); 1677 cmp_ir(code, 0, dst_op.base, SZ_B);
1677 } else { 1678 } else {
1679 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
1680 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1678 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B); 1681 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
1679 } 1682 }
1680 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); 1683 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
1681 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); 1684 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
1682 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); 1685 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1714 } 1717 }
1715 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); 1718 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
1716 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); 1719 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1717 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); 1720 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
1718 if (dst_op.mode == MODE_REG_DIRECT) { 1721 if (dst_op.mode == MODE_REG_DIRECT) {
1722 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1719 cmp_ir(code, 0, dst_op.base, SZ_B); 1723 cmp_ir(code, 0, dst_op.base, SZ_B);
1720 } else { 1724 } else {
1725 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
1726 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1721 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B); 1727 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
1722 } 1728 }
1723 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); 1729 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
1724 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); 1730 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
1725 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); 1731 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1757 } 1763 }
1758 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); 1764 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
1759 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); 1765 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1760 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); 1766 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
1761 if (dst_op.mode == MODE_REG_DIRECT) { 1767 if (dst_op.mode == MODE_REG_DIRECT) {
1768 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1762 cmp_ir(code, 0, dst_op.base, SZ_B); 1769 cmp_ir(code, 0, dst_op.base, SZ_B);
1763 } else { 1770 } else {
1771 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
1772 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1764 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B); 1773 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
1765 } 1774 }
1766 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); 1775 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
1767 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); 1776 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
1768 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); 1777 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));