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Remove old refresh hack that is causing VDPFifoTesting to have a failed test
author Michael Pavone <pavone@retrodev.com>
date Thu, 19 Oct 2023 23:27:57 -0700
parents f8b5142c06aa
children 03e6ac327ba0
comparison
equal deleted inserted replaced
2353:c66e051de8a6 2354:a773b8f09292
672 genesis_context * gen = context->system; 672 genesis_context * gen = context->system;
673 vdp_context * v_context = gen->vdp; 673 vdp_context * v_context = gen->vdp;
674 //printf("acknowledging %d @ %d:%d, vcounter: %d, hslot: %d\n", context->int_ack, context->current_cycle, v_context->cycles, v_context->vcounter, v_context->hslot); 674 //printf("acknowledging %d @ %d:%d, vcounter: %d, hslot: %d\n", context->int_ack, context->current_cycle, v_context->cycles, v_context->vcounter, v_context->hslot);
675 vdp_run_context(v_context, context->current_cycle); 675 vdp_run_context(v_context, context->current_cycle);
676 vdp_int_ack(v_context); 676 vdp_int_ack(v_context);
677 677
678 //the Genesis responds to these exclusively with !VPA which means its a slow 678 //the Genesis responds to these exclusively with !VPA which means its a slow
679 //6800 operation. documentation says these can take between 10 and 19 cycles. 679 //6800 operation. documentation says these can take between 10 and 19 cycles.
680 //actual results measurements seem to suggest it's actually between 9 and 18 680 //actual results measurements seem to suggest it's actually between 9 and 18
681 //Base 68K core has added 4 cycles for a normal int ack cycle already 681 //Base 68K core has added 4 cycles for a normal int ack cycle already
682 //We add 5 + the current cycle count (in 68K cycles) mod 10 to simulate the 682 //We add 5 + the current cycle count (in 68K cycles) mod 10 to simulate the
683 //additional variable delay from the use of the 6800 cycle 683 //additional variable delay from the use of the 6800 cycle
684 uint32_t cycle_count = context->current_cycle / context->options->gen.clock_divider; 684 uint32_t cycle_count = context->current_cycle / context->options->gen.clock_divider;
685 context->current_cycle += 5 + (cycle_count % 10); 685 context->current_cycle += 5 + (cycle_count % 10);
686 686
687 return context; 687 return context;
688 } 688 }
689 689
690 static m68k_context * vdp_port_write(uint32_t vdp_port, m68k_context * context, uint16_t value) 690 static m68k_context * vdp_port_write(uint32_t vdp_port, m68k_context * context, uint16_t value)
691 { 691 {
779 vdp_test_port_write(gen->vdp, value); 779 vdp_test_port_write(gen->vdp, value);
780 } 780 }
781 781
782 //refresh may have happened while we were waiting on the VDP, 782 //refresh may have happened while we were waiting on the VDP,
783 //so advance refresh_counter but don't add any delays 783 //so advance refresh_counter but don't add any delays
784 if (vdp_port >= 4 && vdp_port < 8 && v_context->cycles != before_cycle) { 784 gen_update_refresh_no_wait(context);
785 gen->refresh_counter = 0;
786 gen->last_sync_cycle = context->current_cycle;
787 } else {
788 gen_update_refresh_no_wait(context);
789 }
790 return context; 785 return context;
791 } 786 }
792 787
793 static m68k_context * vdp_port_write_b(uint32_t vdp_port, m68k_context * context, uint8_t value) 788 static m68k_context * vdp_port_write_b(uint32_t vdp_port, m68k_context * context, uint8_t value)
794 { 789 {