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Initial work on emulating the YMZ263B in the Copera
author Michael Pavone <pavone@retrodev.com>
date Fri, 23 Feb 2024 01:16:38 -0800
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children a25e8f304343
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2459:cb62730d5c99 2460:a4f8fa24764b
1 #include <string.h>
2 #include "ymz263b.h"
3 #include "backend.h"
4
5 enum {
6 YMZ_SELT,
7 YMZ_LSI_TEST,
8 YMZ_TIMER0_LOW,
9 YMZ_TIMER0_HIGH,
10 YMZ_TIMER_BASE,
11 YMZ_TIMER1,
12 YMZ_TIMER2_LOW,
13 YMZ_TIMER2_HIGH,
14 YMZ_TIMER_CTRL,
15 YMZ_PCM_PLAY_CTRL,
16 YMZ_PCM_VOL,
17 YMZ_PCM_DATA,
18 YMZ_PCM_CTRL,
19 YMZ_MIDI_CTRL,
20 YMZ_MIDI_DATA
21 };
22
23 //YMZ_SELT
24 #define BIT_SELT 0x01
25
26 //YMZ_TIMER_CTRL
27 #define BIT_ST0 0x01
28 #define BIT_ST1 0x02
29 #define BIT_ST2 0x04
30 #define BIT_STBC 0x08
31 #define BIT_T0_MSK 0x10
32 #define BIT_T1_MSK 0x20
33 #define BIT_T2_MSK 0x40
34
35 #define TIMER_RUN_MASK (BIT_ST0|BIT_ST1|BIT_ST2)
36 #define TIMER_INT_MASK (BIT_T0_MSK|BIT_T1_MSK|BIT_T2_MSK)
37
38 //YMZ_PCM_PLAY_CTRL
39 #define BIT_ADP_RST 0x80
40
41 //YMZ_MIDI_CTRL
42 #define BIT_MSK_RRQ 0x01
43 #define BIT_MRC_RST 0x02
44 #define BIT_MSK_TRQ 0x04
45 #define BIT_MTR_RST 0x08
46 #define BIT_MSK_MOV 0x10
47 #define BIT_MSK_POV 0x20
48
49 #define STATUS_FIF1 0x01
50 #define STATUS_FIF2 0x02
51 #define STATUS_RRQ 0x04
52 #define STATUS_TRQ 0x08
53 #define STATUS_T0 0x10
54 #define STATUS_T1 0x20
55 #define STATUS_T2 0x40
56 #define STATUS_OV 0x80
57
58 #define MIDI_BYTE_DIVIDER 170
59
60 #define FIFO_EMPTY 255
61 void ymz263b_init(ymz263b *ymz, uint32_t clock_divider)
62 {
63 memset(ymz, 0, sizeof(*ymz));
64 ymz->clock_inc = clock_divider * 32;
65 ymz->base_regs[YMZ_SELT] = 1;
66 ymz->pcm[0].regs[0] = BIT_ADP_RST;
67 ymz->pcm[1].regs[0] = BIT_ADP_RST;
68 ymz->midi_regs[0] = BIT_MTR_RST | BIT_MRC_RST;
69 ymz->midi_trs.read = ymz->midi_rcv.read = FIFO_EMPTY;
70 ymz->status = 0;
71 }
72
73 static uint8_t fifo_empty(ymz_midi_fifo *fifo)
74 {
75 return fifo->read == FIFO_EMPTY;
76 }
77
78 static uint8_t fifo_read(ymz_midi_fifo *fifo)
79 {
80 uint8_t ret = fifo->fifo[fifo->read++];
81 fifo->read &= 15;
82 if (fifo->read == fifo->write) {
83 fifo->read = FIFO_EMPTY;
84 }
85 return ret;
86 }
87
88 static uint8_t fifo_write(ymz_midi_fifo *fifo, uint8_t value)
89 {
90 uint8_t overflow = fifo->read == fifo->write;
91 if (fifo->read == FIFO_EMPTY) {
92 fifo->read = fifo->write;
93 }
94 fifo->fifo[fifo->write++] = value;
95 fifo->write &= 15;
96 return overflow;
97 }
98
99 static uint8_t fifo_size(ymz_midi_fifo *fifo)
100 {
101 if (fifo->read == FIFO_EMPTY) {
102 return 0;
103 }
104 if (fifo->read == fifo->write) {
105 return 16;
106 }
107 return (fifo->write - fifo->read) & 15;
108 }
109
110 void ymz263b_run(ymz263b *ymz, uint32_t target_cycle)
111 {
112 uint8_t timer_ctrl = ymz->base_regs[YMZ_TIMER_CTRL];
113 for (; ymz->cycle < target_cycle; ymz->cycle += ymz->clock_inc)
114 {
115 if (timer_ctrl & BIT_ST0) {
116 if (ymz->timers[0]) {
117 ymz->timers[0]--;
118 } else {
119 ymz->timers[0] = ymz->base_regs[YMZ_TIMER0_HIGH] << 8 | ymz->base_regs[YMZ_TIMER0_LOW];
120 ymz->status |= STATUS_T0;
121 }
122 }
123 if (timer_ctrl & BIT_STBC) {
124 if (ymz->timers[3]) {
125 ymz->timers[3]--;
126 } else {
127 ymz->timers[3] = ymz->base_regs[YMZ_TIMER1] << 8 & 0xF00;
128 ymz->timers[3] |= ymz->base_regs[YMZ_TIMER_BASE];
129
130 if (timer_ctrl & BIT_ST1) {
131 if (ymz->timers[1]) {
132 ymz->timers[1]--;
133 } else {
134 ymz->timers[1] = ymz->base_regs[YMZ_TIMER1] >> 4;
135 ymz->status |= STATUS_T1;
136 }
137 }
138
139 if (timer_ctrl & BIT_ST2) {
140 if (ymz->timers[2]) {
141 ymz->timers[2]--;
142 } else {
143 ymz->timers[2] = ymz->base_regs[YMZ_TIMER2_HIGH] << 8 | ymz->base_regs[YMZ_TIMER2_LOW];
144 ymz->status |= STATUS_T2;
145 }
146 }
147 }
148 }
149 if (!(ymz->midi_regs[0] & BIT_MTR_RST) && !fifo_empty(&ymz->midi_trs)) {
150 if (ymz->midi_transmit) {
151 --ymz->midi_transmit;
152 } else {
153 ymz->midi_transmit = MIDI_BYTE_DIVIDER - 1;
154 //TODO: send this byte to MIDI device
155 uint8_t byte = fifo_read(&ymz->midi_trs);
156 printf("MIDI Transmit: %X\n", byte);
157 if (fifo_empty(&ymz->midi_trs)) {
158 ymz->status |= STATUS_TRQ;
159 }
160 }
161 }
162 }
163 }
164
165 uint32_t ymz263b_next_int(ymz263b *ymz)
166 {
167 //TODO: Handle FIFO and MIDI receive interrupts
168 uint8_t enabled_ints = (~ymz->base_regs[YMZ_TIMER_CTRL]) & TIMER_INT_MASK;
169 if (!(ymz->base_regs[YMZ_MIDI_CTRL] & (BIT_MTR_RST|BIT_MSK_TRQ))) {
170 enabled_ints |= STATUS_TRQ;
171 }
172 if (!enabled_ints) {
173 return CYCLE_NEVER;
174 }
175 //Handle currently pending interrupts
176 if (enabled_ints & ymz->status) {
177 return ymz->cycle;
178 }
179 uint32_t ret = CYCLE_NEVER;
180 if (enabled_ints & STATUS_TRQ) {
181 uint8_t bytes = fifo_size(&ymz->midi_trs);
182 if (bytes) {
183 ret = ymz->cycle + (ymz->midi_transmit + 1) * ymz->clock_inc;
184 if (bytes > 1) {
185 ret += MIDI_BYTE_DIVIDER * ymz->clock_inc * (bytes - 1);
186 }
187 }
188 }
189 enabled_ints >>= 4;
190 //If timers aren't already expired, interrupts can't fire unless the timers are enabled
191 enabled_ints &= ymz->base_regs[YMZ_TIMER_CTRL];
192 if (!(ymz->base_regs[YMZ_TIMER_CTRL] & BIT_STBC)) {
193 //Timer 1 and Timer 2 depend on the base timer
194 enabled_ints &= 1;
195 }
196 if (enabled_ints & BIT_ST0) {
197 uint32_t t0 = ymz->cycle + (ymz->timers[0] + 1) * ymz->clock_inc;
198 if (t0 < ret) {
199 ret = t0;
200 }
201 }
202 if (enabled_ints & (BIT_ST1|BIT_ST2)) {
203 uint32_t base = ymz->cycle + (ymz->timers[3] + 1) * ymz->clock_inc;
204 if (base < ret) {
205 uint32_t load = (ymz->base_regs[YMZ_TIMER1] << 8 & 0xF00) | ymz->base_regs[YMZ_TIMER_BASE];
206 if (enabled_ints & BIT_ST1) {
207 uint32_t t1 = ymz->timers[1] * (load + 1) * ymz->clock_inc;
208 if (t1 < ret) {
209 ret = t1;
210 }
211 }
212 if (enabled_ints & BIT_ST2) {
213 uint32_t t2 = ymz->timers[2] * (load + 1) * ymz->clock_inc;
214 if (t2 < ret) {
215 ret = t2;
216 }
217 }
218 }
219 }
220 return ret;
221 }
222
223 void ymz263b_address_write(ymz263b *ymz, uint8_t value)
224 {
225 ymz->address = value;
226 }
227
228 void ymz263b_data_write(ymz263b *ymz, uint32_t channel, uint8_t value)
229 {
230 if (channel) {
231 if (ymz->address >= YMZ_PCM_PLAY_CTRL && ymz->address < YMZ_MIDI_CTRL) {
232 ymz->pcm[1].regs[ymz->address - YMZ_PCM_PLAY_CTRL] = value;
233 }
234 } else {
235 if (ymz->address < YMZ_PCM_PLAY_CTRL) {
236 ymz->base_regs[ymz->address] = value;
237 } else if (ymz->address < YMZ_MIDI_CTRL) {
238 ymz->pcm[0].regs[ymz->address - YMZ_PCM_PLAY_CTRL] = value;
239 } else {
240 ymz->midi_regs[ymz->address - YMZ_MIDI_CTRL] = value;
241 if (ymz->address == YMZ_MIDI_DATA) {
242 ymz->status &= ~STATUS_TRQ;
243 if (fifo_empty(&ymz->midi_trs)) {
244 ymz->midi_transmit = MIDI_BYTE_DIVIDER - 1;
245 }
246 fifo_write(&ymz->midi_trs, value);
247 }
248 }
249 }
250 }
251
252 uint8_t ymz263b_data_read(ymz263b *ymz, uint32_t channel)
253 {
254 //TODO: Supposedly only a few registers are actually readable
255 if (channel) {
256 if (ymz->address >= YMZ_PCM_PLAY_CTRL && ymz->address < YMZ_MIDI_CTRL) {
257 return ymz->pcm[1].regs[ymz->address - YMZ_PCM_PLAY_CTRL];
258 }
259 } else {
260 if (ymz->address < YMZ_PCM_PLAY_CTRL) {
261 return ymz->base_regs[ymz->address];
262 } else if (ymz->address < YMZ_MIDI_CTRL) {
263 return ymz->pcm[0].regs[ymz->address - YMZ_PCM_PLAY_CTRL];
264 } else {
265 return ymz->midi_regs[ymz->address - YMZ_MIDI_CTRL];
266 }
267 }
268 return 0XFF;
269 }
270
271 uint8_t ymz263b_status_read(ymz263b *ymz)
272 {
273 uint8_t ret = ymz->status;
274 ymz->status = 0;//&= ~(STATUS_T0|STATUS_T1|STATUS_T2);
275 return ret;
276 }