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comparison z80_to_x86.c @ 1061:9b5bb50098d2

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Implemented INIR
author Michael Pavone <pavone@retrodev.com>
date Mon, 01 Aug 2016 19:18:50 -0700
parents 56713dac6a69
children 779acbfb74d0
comparison
equal deleted inserted replaced
1060:56713dac6a69 1061:9b5bb50098d2
2391 } else { 2391 } else {
2392 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B); 2392 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
2393 } 2393 }
2394 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); 2394 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
2395 break; 2395 break;
2396 /*case Z80_INIR: 2396 case Z80_INIR: {
2397 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
2398 //read from IO (C)
2399 zreg_to_native(opts, Z80_BC, opts->gen.scratch1);
2400 call(code, opts->read_io);//T states 3
2401
2402 //undocumented N flag behavior
2403 //flag set on bit 7 of value written
2404 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
2405 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N));
2406 //save value to be written for flag calculation, as the write func does not
2407 //guarantee that it's preserved across the call
2408 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_B);
2409
2410 //write to (HL)
2411 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
2412 call(code, opts->write_8);//T states 4
2413 cycles(&opts->gen, 1);
2414
2415 //increment HL
2416 if (opts->regs[Z80_HL] >= 0) {
2417 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
2418 } else {
2419 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
2420 }
2421 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch1, SZ_B);
2422 if (opts->regs[Z80_C] >= 0) {
2423 add_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
2424 } else {
2425 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_C), opts->gen.scratch1, SZ_B);
2426 }
2427 add_ir(code, 1, opts->gen.scratch1, SZ_B);
2428 //undocumented C and H flag behavior
2429 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
2430 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
2431 //decrement B
2432 if (opts->regs[Z80_B] >= 0) {
2433 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
2434 mov_rrdisp(code, opts->regs[Z80_B], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
2435 } else {
2436 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
2437 }
2438 //undocumented Z and S flag behavior, set based on decrement of B
2439 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
2440 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
2441 //crazy undocumented P/V flag behavior
2442 and_ir(code, 7, opts->gen.scratch1, SZ_B);
2443 if (opts->regs[Z80_B] >= 0) {
2444 //deal with silly x86-64 restrictions on *H registers
2445 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
2446 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
2447 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
2448 } else {
2449 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
2450 }
2451 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
2452 if (opts->regs[Z80_B] >= 0) {
2453 cmp_ir(code, 0, opts->regs[Z80_B], SZ_B);
2454 } else {
2455 cmp_irdisp(code, 0, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
2456 }
2457 code_ptr done = code->cur+1;
2458 jcc(code, CC_Z, code->cur+2);
2459 cycles(&opts->gen, 5);
2460 jmp(code, start);
2461 *done = code->cur - (done + 1);
2462 break;
2463 }
2464 /*
2397 case Z80_IND: 2465 case Z80_IND:
2398 case Z80_INDR:*/ 2466 case Z80_INDR:*/
2399 case Z80_OUT: 2467 case Z80_OUT:
2400 if (inst->reg == Z80_A) { 2468 if (inst->reg == Z80_A) {
2401 num_cycles += 3; 2469 num_cycles += 3;