Mercurial > repos > blastem
comparison vdp.c @ 479:863e868752cf
Implement funny behavior for DMA fill to CRAM and VSRAM. Return VSRAM address 0 for reads to VSRAM at >= 40
author | Mike Pavone <pavone@retrodev.com> |
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date | Tue, 17 Sep 2013 00:42:49 -0700 |
parents | 2e4a4188cfb0 |
children | 0737953132ad |
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478:2e4a4188cfb0 | 479:863e868752cf |
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419 return; | 419 return; |
420 } | 420 } |
421 break; | 421 break; |
422 case CRAM_WRITE: { | 422 case CRAM_WRITE: { |
423 //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1)); | 423 //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1)); |
424 write_cram(context, start->address, start->value); | 424 write_cram(context, start->address, start->partial == 2 ? context->fifo[context->fifo_write].value : start->value); |
425 break; | 425 break; |
426 } | 426 } |
427 case VSRAM_WRITE: | 427 case VSRAM_WRITE: |
428 if (((start->address/2) & 63) < VSRAM_SIZE) { | 428 if (((start->address/2) & 63) < VSRAM_SIZE) { |
429 //printf("VSRAM Write: %X to %X\n", start->value, context->address); | 429 //printf("VSRAM Write: %X to %X\n", start->value, context->address); |
430 context->vsram[(start->address/2) & 63] = start->value; | 430 context->vsram[(start->address/2) & 63] = start->partial == 2 ? context->fifo[context->fifo_write].value : start->value; |
431 } | 431 } |
432 | 432 |
433 break; | 433 break; |
434 } | 434 } |
435 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1); | 435 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1); |
1595 break; | 1595 break; |
1596 case CRAM_READ: | 1596 case CRAM_READ: |
1597 value = context->cram[(context->address/2) & (CRAM_SIZE-1)] & CRAM_BITS; | 1597 value = context->cram[(context->address/2) & (CRAM_SIZE-1)] & CRAM_BITS; |
1598 value |= context->fifo[context->fifo_write].value & ~CRAM_BITS; | 1598 value |= context->fifo[context->fifo_write].value & ~CRAM_BITS; |
1599 break; | 1599 break; |
1600 case VSRAM_READ: | 1600 case VSRAM_READ: { |
1601 if (((context->address / 2) & 63) < VSRAM_SIZE) { | 1601 uint16_t address = (context->address /2) & 63; |
1602 value = context->vsram[(context->address / 2) & 63] & VSRAM_BITS; | 1602 if (address >= VSRAM_SIZE) { |
1603 value |= context->fifo[context->fifo_write].value & VSRAM_DIRTY_BITS; | 1603 address = 0; |
1604 } | 1604 } |
1605 break; | 1605 value = context->vsram[address] & VSRAM_BITS; |
1606 value |= context->fifo[context->fifo_write].value & VSRAM_DIRTY_BITS; | |
1607 break; | |
1608 } | |
1606 } | 1609 } |
1607 context->address += context->regs[REG_AUTOINC]; | 1610 context->address += context->regs[REG_AUTOINC]; |
1608 return value; | 1611 return value; |
1609 } | 1612 } |
1610 | 1613 |